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Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 187-191
A.E. de la Serna , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
M.A. Soderstrand , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
ABSTRACT
In this paper, we investigate the trade off between filter order and bits of coefficient precision in fixed-coefficient FIR digital filters utilizing canonical signed digit (CSD) coefficient representation. We demonstrate that the use of optimized CSD coefficients is often the only method for which many practical FIR filters can be prototyped on a single FPGA in today's technology. Due to finite FPGA resources, our resulting analysis of filter-length, word-length, and CSD bit optimization provides an indication of whether a desired filter performance can be obtained with a specific FPGA logic capacity. We develop a MATLAB algorithm for determining the optimum trade-off between FIR filter length and bits of precision of the coefficients in FIR digital filters.<>
INDEX TERMS
FIR filters, field programmable gate arrays, application specific integrated circuits, roundoff errors, logic design
CITATION

A. de la Serna and M. Soderstrand, "Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 187-191.
doi:10.1109/ACSSC.1994.471442
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