Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)

Pacific Grove, CA, USA

Oct. 31, 1994 to Nov. 2, 1994

ISSN: 1058-6393

ISBN: 0-8186-6405-3

pp: 182-186

H.R. Srinivas , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

ABSTRACT

Redundant arithmetic number systems are gaining popularity in computationally intensive environments particularly because of the carry-free addition/subtraction properties they possess. This property has enabled arithmetic operations such as addition, multiplication, division, square root, etc., to be performed much faster than with conventional binary number systems. In this paper, some of the recent contributions to the area of design of redundant arithmetic based addition, multiplication, division, and square root algorithms and architectures are briefly discussed. Also, only the use of bit/digit-parallel implementation for architectures is discussed so that the enhancement in speed through the use of redundant arithmetic becomes immediately apparent as opposed to the use of bit/digit-serial architectures, where the primary justification for their use is to conserve area. A new radix 2 division algorithm using over-redundant radix 2 quotient digits and requiring a 2 digit quotient selection function is also presented.<>

INDEX TERMS

computational complexity, redundant number systems, digital arithmetic, parallel processing

CITATION

H. Srinivas and K. Parhi, "Computer arithmetic architectures with redundant number systems,"

*Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC)*, Pacific Grove, CA, USA, 1995, pp. 182-186.

doi:10.1109/ACSSC.1994.471441

CITATIONS