The Community for Technology Leaders
Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers (1994)
Pacific Grove, CA, USA
Oct. 31, 1994 to Nov. 2, 1994
ISSN: 1058-6393
ISBN: 0-8186-6405-3
pp: 172-176
Yuang-Ming Hsu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
ABSTRACT
Fast Fourier transform (FFT) arrays with built-in error correction are proposed. A time shared TMR scheme is used to achieve the error correcting capability. A quarter of the original FFT array is triplicated and voted in each stage. Therefore the hardware complexity of the error correcting FFT array is a little more than 75% of the original FFT array. This is significant since the error correcting design is smaller than the original. The price for this hardware reduction is that the delay time increases by a factor of 4. However, the throughput penalty can be minimized by pipelining. A technology-independent gate-level analysis of hardware complexity and delay time is included.<>
INDEX TERMS
error correction, fast Fourier transforms, parallel architectures, computational complexity, delays, pipeline processing, signal processing, VLSI, digital integrated circuits, digital signal processing chips
CITATION

Yuang-Ming Hsu and E. Swartzlander, "FFT arrays with built-in error correction," Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers(ACSSC), Pacific Grove, CA, USA, 1995, pp. 172-176.
doi:10.1109/ACSSC.1994.471439
91 ms
(Ver 3.3 (11022016))