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2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013) (2013)
Rohtak
April 6, 2013 to April 7, 2013
ISSN: 2327-0632
ISBN: 978-1-4673-5965-8
pp: 337-342
ABSTRACT
In the present work, improved designs for five-stage voltage controlled ring oscillators (VCO) with reverse body bias and SAL technique have been presented to improve the performance parameter. First VCO design with inverter based delay cell shows frequency variation [3.9-1.89] MHz with SAL technique and Second design with varying PMOS and NMOS substrate bias from [0.6-1.1] V shows frequency variation of [6.62-3.0] GHz. The proposed five stages VCO ring oscillator is implemented in 45nm cadence virtuoso environment provides high oscillation frequency (GHz) provide less delay (0.21psec), minimum phase noise (179.1dBc/Hz) and lower leakage power (1.23pw) with reverse substrate bias technique.
INDEX TERMS
CMOS integrated circuits, delays, phase noise, voltage-controlled oscillators
CITATION

A. Shrivastava, S. Khandelwal and S. Akashe, "Performance Evaluation of Five Stage VCO Ring Oscillator with Reverse Substrate Bias and SAL Technique Using Nanoscale CMOS Technology," 2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013)(ACCT), Rohtak, 2013, pp. 337-342.
doi:10.1109/ACCT.2013.78
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