2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013) (2013)
April 6, 2013 to April 7, 2013
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACCT.2013.76
In modern digital VLSI design, domino logic style circuits are widely used. The CMOS domino logic circuit dissipates very low standby power and exhibits less area. We design a comparator circuit which uses footed domino logic and also implement a current mirror circuit in the design, to enhance the speed of the comparator. This paper emphasizes a CMOS comparator design to detect full match or mismatch of the binary input. The proposed design consumes low leakage power and had a higher speed, than other circuit. The delay, leakage power and average power of the proposed CMOS Comparator circuit have also been calculated and then it is compared with the Footed Domino Logic Comparator circuit with same parameter. The circuit has been simulated in 45nm CMOS technology on Cadence Tool for high fan-ins (4, 8, 16, 32& 64 bits).
circuit simulation, CMOS logic circuits, comparators (circuits), current mirrors, integrated circuit design, logic design, power consumption, VLSI
U. Soni, A. Vidyarthi and S. Akashe, "Design of High Speed and Leakage Tolerant CMOS Comparator in UDSM Technology," 2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013)(ACCT), Rohtak, 2013, pp. 326-329.