2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013) (2013)
April 6, 2013 to April 7, 2013
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ACCT.2013.72
In this paper we design and optimized the low power and high speed 3 bit flash Analog-to-Digital Converter (ADC) using 45 nm technology. For high speed application Resolution, speed and power are optimized for implemented ADC. High integrated flash ADC is designed at three bit precision with operating voltage in range of 700 mV to 1V. This paper also describe the reduction in size of flash ADC and increase bit size of ADC using folding technique. Interpolation factor of 4 is introduced to reduce the comparators and resisters for generation of reference voltage. Interpolation technique reduces input capacitance, delay and increase the bandwidth of input signal. Lower leakage of 17.76 pW and high speed with minimum delay of 14.25 μs is achieved using folding technique. A noise of 0.86 μ dB and maximum SNR of 59 dB is reported in present paper. Folding and interpolation ADC is best suited for ultra low application.
analogue-digital conversion, interpolation
S. Mishra, A. Vidyarthi and S. Akashe, "A Novel Folding Technique for 3 Bit Flash ADC in Nanoscale," 2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013)(ACCT), Rohtak, 2013, pp. 307-311.