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2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013) (2013)
Rohtak
April 6, 2013 to April 7, 2013
ISSN: 2327-0632
ISBN: 978-1-4673-5965-8
pp: 166-170
ABSTRACT
Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Sub-threshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.
INDEX TERMS
MOSFET, SRAM chips
CITATION

V. Sikarwar, S. Khandelwal and S. Akashe, "Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET," 2013 Third International Conference on Advanced Computing & Communication Technologies (ACCT 2013)(ACCT), Rohtak, 2013, pp. 166-170.
doi:10.1109/ACCT.2013.41
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