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Canberra, Australia

Jan. 31, 2000 to Feb. 3, 2000

ISBN: 0-7695-0512-0

pp: 9

Wanming Chu , University of Aizu

Yamin Li , University of Aizu

ABSTRACT

Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fully-pipelined n-select implementations (nS-Root) based on a non-restoring-remainder square root algorithm. The nS-Root uses a parallel array of carry-save adders (CSAs). For a square root bit calculation, a CSA is used once. This means that the calculations can be fully pipelined. It also uses the n-way root-select technique to speedup the square root calculation. The cost/performance evaluation shows that n=2 or n=2.5 is a suitable solution for designing a high-speed fully pipelined square root unit while keeping the low-cost.

CITATION

Wanming Chu,
Yamin Li,
"Cost/Performance Tradeoff of n-Select Square Root Implementations",

*ACAC*, 2000, Australasian Computer Architecture Conference, Australasian Computer Architecture Conference 2000, pp. 9, doi:10.1109/ACAC.2000.824317