The Community for Technology Leaders
Computer-Aided Design, International Conference on (2006)
San Jose, CA
Nov. 5, 2006 to Nov. 9, 2006
ISSN: 1092-3152
TABLE OF CONTENTS
Papers

Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design (Abstract)

Changyun Zhu , Dept. of Electr. & Comput. Eng., Queen's Univ., Kingston, Ont.
Yonghong Yang , Dept. of Electr. & Comput. Eng., Queen's Univ., Kingston, Ont.
pp. 575-582

Foreword (PDF)

pp. 8

ICCAD-2006 Awards (Abstract)

pp. 9

Monday Keynote: An Industry in Transition: Opportunities and Challenges in Next-Generation Microprocessor Design (PDF)

Phil Hester , Corporate Vice President and Chief Technology Officer AMD, Austin, TX
pp. 10

Wednesday Keynote: Innovation in Electronic Design Automation (PDF)

Leon Stok , Director of Electronic Design Automation, IBM Corp., Hopewell Junction, NY
pp. 10

Table of Contents (PDF)

pp. 18-30

Author Index (PDF)

pp. 31-40

Copyright page (PDF)

pp. 41

Dynamic Power Management Using Machine Learning (Abstract)

G. Dhiman , Dept. of Comput. Sci.&Eng., California Univ., San Diego, CA
T.S. Rosing , Dept. of Comput. Sci.&Eng., California Univ., San Diego, CA
pp. 747-754

Stepping Forward with Interpolants in Unbounded Model Checking (Abstract)

S. Quer , Dip. di Automatica e Informatica, Politecnico di Torino, Turin
G. Cabodi , Dip. di Automatica e Informatica, Politecnico di Torino, Turin
M. Murciano , Dip. di Automatica e Informatica, Politecnico di Torino, Turin
S. Nocco , Dip. di Automatica e Informatica, Politecnico di Torino, Turin
pp. 772-778

Automatic Memory Reductions for RTL Model Verification (Abstract)

P. Manoliost , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA
pp. 786-793

Accelerating High-level Bounded Model Checking (Abstract)

M.K. Ganai , NEC Labs. America, Princeton, NJ
A. Gupta , NEC Labs. America, Princeton, NJ
pp. 794-801

Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs (Abstract)

J. Ho , EE Dept., California Univ., Los Angeles, CA
null Hao Yu , EE Dept., California Univ., Los Angeles, CA
null Lei He , EE Dept., California Univ., Los Angeles, CA
pp. 802-808

Yield Prediction for 3D Capacitive Interconnections (Abstract)

P. Zoffoli , ARCES-Univ. of Bologna
A. Fazzi , ARCES-Univ. of Bologna
L. Magagni , ARCES-Univ. of Bologna
M. De Dominicis , ARCES-Univ. of Bologna
pp. 809-814

Layer Minimization of Escape Routing in Area Array Packaging (Abstract)

null Rui Shi , Dept. of Comput. Sci.&Eng., Univ. of California, San Diego, CA
null Chung-Kuan Cheng , Dept. of Comput. Sci.&Eng., Univ. of California, San Diego, CA
null Renshen Wang , Dept. of Comput. Sci.&Eng., Univ. of California, San Diego, CA
pp. 815-819

Network Coding for Routability Improvement in VLSI (Abstract)

K. Gulati , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
A. Sprintson , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
N. Jayakumar , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
S.P. Khatri , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 820-823

From Micro to Nano: MEMS as an interface to the nano world (Abstract)

B.E. Boser , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA
pp. 824-825

CMOS-MEMS Integration: Why, How and What? (Abstract)

A. Witvrouw , SPDT/MEMS, IMEC, Leuven
pp. 826-827

Molecular Organic Electronic Circuits (Abstract)

V. Bulovi , Microsystems Technol. Labs., Cambridge, MA
pp. 830-831

Organic Electronic Device Modeling at the Nanoscale (Abstract)

C. Madigan , Lab of Org. Opt.&Electron., MIT, Cambridge, MA
pp. 832-833

Variability and yield improvement: rules, models, and characterization (Abstract)

K.L. Shepard , Columbia Integrated Syst. Lab, Columbia Univ., New York, NY
pp. 834-835

Improvements to Combinational Equivalence Checking (Abstract)

R. Brayton , Dept. of Electron. Eng.&Comput. Sci., California Univ., Berkeley, CA
A. Mishchenko , Dept. of Electron. Eng.&Comput. Sci., California Univ., Berkeley, CA
S. Chatterjee , Dept. of Electron. Eng.&Comput. Sci., California Univ., Berkeley, CA
pp. 836-843

SMT(CLU): A Step toward Scalability in System Verification (Abstract)

H.M. Sheini , Electr. Eng.&Comput. Sci. Dept., Michigan Univ., Ann Arbor, MI
pp. 844-851

Solving the Minimum-Cost Satisfiability Problem Using SAT Based Branch-and-Bound Search (Abstract)

S. Malik , Dept. of Electr. Eng., Princeton Univ., NJ
null Zhaohui Fu , Dept. of Electr. Eng., Princeton Univ., NJ
pp. 852-859

Veri cation Through the Principle of Least Astonishment (Abstract)

V. Bertacco , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI
B. Isaksen , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI
pp. 860-867

Performance-Oriented Statistical Parameter Reduction of Parameterized Systems via Reduced Rank Regression (Abstract)

null Peng Li , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Zhuo Feng , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 868-875

Robust Estimation of Parametric Yield under Limited Descriptions of Uncertainty (Abstract)

M. Orshansky , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
null Wei-Shen Wang , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
pp. 884-890

From molecular interactions to gates: a systematic approach (Abstract)

J. Carmona , Univ. Politecnica Catalunya, Barcelona
J. Cortadella , Univ. Politecnica Catalunya, Barcelona
pp. 891-898

A Spectrally Accurate Integral Equation Solver for Molecular Surface Electrostatics (Abstract)

J. White , Dept. of Electr. Eng.&Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA
null Shih-Hsien Kuo , Dept. of Electr. Eng.&Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA
pp. 899-906

Using CAD to Shape Experiments in Molecular QCA (Abstract)

M. Niemier , Georgia Inst. of Tech., Atlanta, GA
pp. 907-914

Stable and Compact Inductance Modeling of 3-D Interconnect Structures (Abstract)

null Hong Li , Sch. of Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
V. Balakrishnan , Sch. of Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
null Cheng-Kok Koh , Sch. of Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
pp. 1-6

A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits (Abstract)

null Yiyu Shi , EE Dept., California Univ., Los Angeles, CA
null Hao Yu , EE Dept., California Univ., Los Angeles, CA
null Lei He , EE Dept., California Univ., Los Angeles, CA
pp. 7-12

Fullwave Volumetric Maxwell solver using Conduction Modes (Abstract)

S. Ortiz , Mentor Graphics Ireland French Branch, Ismier
R. Suaya , Mentor Graphics Ireland French Branch, Ismier
pp. 13-18

Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization (Abstract)

A.K. Singh , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
M. Orshansky , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
M. Mani , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
pp. 19-26

State Re-Encoding for Peak Current Minimization (Abstract)

null Chia-Ming Chang , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li
null Shih-Hsu Huang , Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li
pp. 33-38

A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering (Abstract)

D. Blaauw , EECS Dept., Michigan Univ., Ann Arbor, MI
S.H. Kulkarni , EECS Dept., Michigan Univ., Ann Arbor, MI
D. Sylvester , EECS Dept., Michigan Univ., Ann Arbor, MI
pp. 39-46

Practical Variation-Aware Interconnect Delay and Slew Analysis for Statistical Timing Verification (Abstract)

null Xiaoji Ye , Dept. of ECE, Texas A&M Univ., College Station, TX
null Peng Li , Dept. of ECE, Texas A&M Univ., College Station, TX
pp. 54-59

Analysis and Modeling of CD Variation for Statistical Static Timing (Abstract)

K. Chopra , Michigan Univ., Ann Arbor, MI
B. Cline , Michigan Univ., Ann Arbor, MI
D. Blaauw , Michigan Univ., Ann Arbor, MI
pp. 60-66

On Bounding the Delay of a Critical Path (Abstract)

L.-C. Wang , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
L. Lee , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
pp. 81-88

A Delay Fault Model for At-Speed Fault Simulation and Test Generation (Abstract)

I. Pomeranz , Sch. of Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
pp. 89-95

Efficient Boolean Characteristic Function for Fast Timed ATPG (Abstract)

null Yu-Min Kuo , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
null Yue-Lung Chang , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
null Shih-Chieh Chang , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
pp. 96-99

Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts (Abstract)

null Shun-Yen Lu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
null Jing-Jia Liou , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
null Pei-Ying Hsieh , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
pp. 100-106

Fast Decap Allocation Based on Algebraic Multigrid (Abstract)

null Cheng Zhuo , Dept. of Inf. Sci.&Electron. Eng., Zhejiang Univ., Hangzhou
pp. 107-111

Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification (Abstract)

N. Evmorfopoulos , Dept. of Comput.&Commun. Eng., Thessaly Univ., Volos
G. Stamoulis , Dept. of Comput.&Commun. Eng., Thessaly Univ., Volos
D. Karampatzakis , Dept. of Comput.&Commun. Eng., Thessaly Univ., Volos
pp. 112-118

Importance of Volume Discretization of Single and Coupled Interconnects (Abstract)

A. Shebaita , Dept. of Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
pp. 119-126

Handling Inductance in Early Power Grid Verification (Abstract)

N.H.A. Ghani , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont.
F.N. Najm , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont.
pp. 127-134

Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs (Abstract)

G.R. Chiu , Toronto Technol. Center, Altera Corp., Toronto, Ont.
S.D. Brown , Toronto Technol. Center, Altera Corp., Toronto, Ont.
D.P. Singh , Toronto Technol. Center, Altera Corp., Toronto, Ont.
V. Manohararajah , Toronto Technol. Center, Altera Corp., Toronto, Ont.
pp. 135-142

Factor Cuts (Abstract)

A. Mishchenko , Dept. of EECS, U. C. Berkeley, CA
R. Brayton , Dept. of EECS, U. C. Berkeley, CA
S. Chatterjee , Dept. of EECS, U. C. Berkeley, CA
pp. 143-150

Cost-aware synthesis of asynchronous circuits based on partial acknowledgement (Abstract)

A. Yakovlev , Sch. of Electr., Electron.&Comput. Eng., Univ. of Newcastle upon Tyne
D. Sokolov , Sch. of Electr., Electron.&Comput. Eng., Univ. of Newcastle upon Tyne
null Yu Zhou , Sch. of Electr., Electron.&Comput. Eng., Univ. of Newcastle upon Tyne
pp. 158-163

Fast Wire Length Estimation by Net Bundling for Block Placement (Abstract)

H. Murata , Fac. of Environ. Eng., Kitakyushu Univ.
T. Yan , Fac. of Environ. Eng., Kitakyushu Univ.
pp. 172-178

Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model (Abstract)

P. Spindler , Inst. of Electron. Design Autom., Technische Univ. Muenchen, Munich
F.M. Johannes , Inst. of Electron. Design Autom., Technische Univ. Muenchen, Munich
pp. 179-186

A High-Quality Mixed-Size Analytical Placer Considering Preplaced Blocks and Density Constraints (Abstract)

null Tung-Chieh Chen , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei
null Zhe-Wei Jiang , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei
null Tien-Chang Hsu , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei
pp. 187-192

Testing Delay Faults in Asynchronous Handshake Circuits (Abstract)

Y. Makris , Dept. of Electr. Eng., Yale Univ., New Haven, CT
null Feng Shi , Dept. of Electr. Eng., Yale Univ., New Haven, CT
pp. 193-197

A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects (Abstract)

M. Tehranipoor , Dept. of Electr.&Comput. Eng., Connecticut Univ.
N. Ahmed , Dept. of Electr.&Comput. Eng., Connecticut Univ.
pp. 198-203

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques (Abstract)

null Quming Zhou , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
M.R. Choudhury , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
K. Mohanram , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
pp. 204-209

Enhanced Error Vector Magnitude (EVM) Measurements for Testing WLAN Transceivers (Abstract)

E. Acar , Duke Univ., Durham, NC
S. Ozev , Duke Univ., Durham, NC
pp. 210-216

A Linear-Time Approach for Static Timing Analysis Covering All Process Corners (Abstract)

S. Onaissi , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont.
F.N. Najm , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont.
pp. 217-224

A Framework for Statistical Timing Analysis using Non-Linear Delay and Slew Models (Abstract)

S. Vrudhula , Dept. of Electr. Eng., Arizona State Univ.
S. Bhardwaj , Dept. of Electr. Eng., Arizona State Univ.
P. Ghanta , Dept. of Electr. Eng., Arizona State Univ.
pp. 225-230

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis (Abstract)

D.Z. Pan , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
null Gi-Joon Nam , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
A.K. Singh , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
M. Orshansky , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
S.R. Nassif , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
A. Ramalingam , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
pp. 231-236

A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis (Abstract)

D. Sylvester , Dept. of Electron. Eng.&Comput. Sci., Michigan Univ.
B. Zhai , Dept. of Electron. Eng.&Comput. Sci., Michigan Univ.
D. Blaauw , Dept. of Electron. Eng.&Comput. Sci., Michigan Univ.
K. Chopra , Dept. of Electron. Eng.&Comput. Sci., Michigan Univ.
pp. 237-243

Cache Miss Clustering for Banked Memory Systems (Abstract)

M. Kandemir , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ.
G. Chen , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ.
O. Ozturk , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ.
pp. 244-250

A Bitmask-based Code Compression Technique for Embedded Systems (Abstract)

P. Mishra , Dept. of Comput.&Inf. Sci.&Eng., Florida Univ., Gainesville, FL
null Seok-Won Seonq , Dept. of Comput.&Inf. Sci.&Eng., Florida Univ., Gainesville, FL
pp. 251-254

Allocation Cost Minimization for Periodic Hard Real-Time Tasks in Energy-Constrained DVS Systems (Abstract)

null Tei-Wei Kuo , Dept. of Comput. Sci.&Inf. Eng., National Taiwan Univ.
null Jian-Jia Chen , Dept. of Comput. Sci.&Inf. Eng., National Taiwan Univ.
pp. 255-260

TP-PPV: Piecewise Nonlinear, Time-Shifted Oscillator Macromodel Extraction For Fast, Accurate PLL Simulation (Abstract)

null Xiaolue Lai , Dept. of Electr.&Comput. Eng., Minnesota Univ., Minneapolis, MN
J. Roychowdhury , Dept. of Electr.&Comput. Eng., Minnesota Univ., Minneapolis, MN
pp. 269-274

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets (Abstract)

C. Myers , Utah Univ., Salt Lake City, UT
D. Walter , Utah Univ., Salt Lake City, UT
N. Seegmiller , Utah Univ., Salt Lake City, UT
S. Little , Utah Univ., Salt Lake City, UT
pp. 275-282

Loop Pipelining for High-Throughput Stream Computation Using Self-Timed Rings (Abstract)

M. Singh , Dept. of Comput. Sci., North Carolina Univ.
J. Hansen , Dept. of Comput. Sci., North Carolina Univ.
G. Gill , Dept. of Comput. Sci., North Carolina Univ.
pp. 289-296

Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation (Abstract)

S.O. Memik , Dept. of Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
null Min Ni , Dept. of Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
pp. 297-302

Guaranteeing Performance Yield in High-Level Synthesis (Abstract)

null Yuan Xie , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA
W.L. Hung , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA
null Xiaoxia Wu , Dept. of Comput. Sci.&Eng., Pennsylvania State Univ., University Park, PA
pp. 303-309

Analytical Modeling of SRAM Dynamic Stability (Abstract)

S. Nassif , Dept. of Electr.&Comput. Eng., Univ. of Texas, Austin, TX
M. Orshansky , Dept. of Electr.&Comput. Eng., Univ. of Texas, Austin, TX
A. Arapostathis , Dept. of Electr.&Comput. Eng., Univ. of Texas, Austin, TX
null Bin Zhang , Dept. of Electr.&Comput. Eng., Univ. of Texas, Austin, TX
pp. 315-322

A High-Level Compact Pattern-Dependent Delay Model for High-Speed Point-to-point Interconnects (Abstract)

M. Momeni , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.
A.G. Ortiz , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.
T. Murgan , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol.
pp. 323-328

Design and CAD Challenges in 45nm CMOS and beyond (Abstract)

D.J. Frank , IBM TJ Watson Res. Center, Yorktown Heights, NY
R. Puri , IBM TJ Watson Res. Center, Yorktown Heights, NY
pp. 329-333

Robust System-Level Design with Analog Platforms (Abstract)

F. De Bernardinis , Dipt. di Ingegneria dell'Informazione, Univ. di Pisa
P. Nuzzo , Dipt. di Ingegneria dell'Informazione, Univ. di Pisa
pp. 334-341

Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts (Abstract)

N. Kohagen , Washington Univ., Seattle, WA
C.-J.R. Shi , Washington Univ., Seattle, WA
S. Bhattacharya , Washington Univ., Seattle, WA
N. Jangkrajarng , Washington Univ., Seattle, WA
null Lihong Zhang , Washington Univ., Seattle, WA
pp. 342-348

Analog Placement with Symmetry and Other Placement Constraints (Abstract)

null Yiu-Cheong Tam , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong
E.F.Y. Young , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong
pp. 349-354

Fast and Accurate Transaction Level Models using Result Oriented Modeling (Abstract)

G. Schirner , Center for Embedded Comput. Syst., California Univ., Irvine, CA
R. Domer , Center for Embedded Comput. Syst., California Univ., Irvine, CA
pp. 363-368

Optimal Memoryless Encoding for Low Power Off-Chip Data Buses (Abstract)

null Yeow Meng Chee , Sch. of Phys.&Math. Sci., Nanyang Technol. Univ., Singapore
pp. 369-374

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs (Abstract)

S. Dutt , Dept. of Electr.&Comput. Eng., Illinois Univ., Chicago, IL
F. Yuan , Dept. of Electr.&Comput. Eng., Illinois Univ., Chicago, IL
V. Suthar , Dept. of Electr.&Comput. Eng., Illinois Univ., Chicago, IL
H. Ren , Dept. of Electr.&Comput. Eng., Illinois Univ., Chicago, IL
pp. 375-382

Voltage Island Aware Floorplanning for Power and Timing Optimization (Abstract)

null Yap-Wen Chang , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Wan-Ping Lee , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Hung-Yi Liu , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
pp. 389-394

Decoupling Capacitor Planning and Sizing For Noise and Leakage Reduction (Abstract)

J. Minz , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
E. Wong , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
null Sung Kyu Lim , Sch. of Electr.&Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
pp. 395-400

A Timing Dependent Power Estimation Framework Considering Coupling (Abstract)

D.E. Khalil , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
null Hai Zhou , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
D. Sinha , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
Y. Ismail , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
pp. 401-407

Algorithms for MIS Vector Generation and Pruning (Abstract)

K.S. Stevens , Electr.&Comput. Eng., Utah Univ., Salt Lake, UT
pp. 408-414

A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power (Abstract)

D.Z. Pan , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
S.X. Shi , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
null Peng Yu , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
pp. 423-428

Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation (Abstract)

null Xiaoyao Liang , Div. of Eng.&Appl. Sci., Harvard Univ., Cambridge, MA
D. Brooks , Div. of Eng.&Appl. Sci., Harvard Univ., Cambridge, MA
pp. 429-436

Thermal Sensor Allocation and Placement for Reconfigurable Systems (Abstract)

S. Mondal , Synopsys, Inc., Mountain View, CA
R. Mukherjee , Synopsys, Inc., Mountain View, CA
S.O. Memik , Synopsys, Inc., Mountain View, CA
pp. 437-442

Performance analysis of concurrent systems with early evaluation (Abstract)

J. Julvez , Univ. Politecnica de Catalunya, Barcelona
J. Cortadella , Univ. Politecnica de Catalunya, Barcelona
pp. 448-455

Near-Term Industrial Perspective of Analog CAD (Abstract)

C. Labrecque , Synopsys, Inc., Mountain View, CA
pp. 456-457

Design Automation for Analog: The Next Generation of Tool Challenges (Abstract)

R.A. Rutenbar , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
pp. 458-460

FastRoute: A Step to Integrate Global Routing into Placement (Abstract)

C. Chu , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
null Min Pan , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
pp. 464-471

Trunk Decomposition Based Global Routing Optimization (Abstract)

D. Jariwala , Dept. of Comput. Sci., Illinois Univ., Chicago, ID
J. Lillis , Dept. of Comput. Sci., Illinois Univ., Chicago, ID
pp. 472-479

Optimizing Yield in Global Routing (Abstract)

D. Muller , Res. Inst. for Discrete Math., Bonn Univ.
pp. 480-486

Wire Density Driven Global Routing for CMP Variation and Timing (Abstract)

D.Z. Pan , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
null Minsik Cho , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX
pp. 487-492

An Analytical Model for Negative Bias Temperature Instability (Abstract)

C.H. Kim , Dept. of Electr.&Comput. Eng., Minnesota Univ.
S.S. Sapatnekar , Dept. of Electr.&Comput. Eng., Minnesota Univ.
S.V. Kumar , Dept. of Electr.&Comput. Eng., Minnesota Univ.
pp. 493-496

Soft Error Derating Computation in Sequential Circuits (Abstract)

H. Asadi , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
M.B. Tahoori , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
pp. 497-501

Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection (Abstract)

R.R. Rao , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
D. Sylvester , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
D. Blaauw , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
pp. 502-509

Current Path Analysis for Electrostatic Discharge Protection (Abstract)

null Hung-Yi Liu , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Yao-Wen Chang , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Szu-Jui Chou , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Sy-Yen Kuon , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Chih-Hung Liu , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Chung-Wei Lin , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
null Wei-Ting Tu , Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
pp. 510-515

System-Wide Energy Minimization for Real-Time Tasks: Lower Bound and Approximation (Abstract)

null Xiliang Zhong , Dept. of Electr.&Comput. Eng., Wayne State Univ., Detroit, MI
null Cheng-Zhong Xu , Dept. of Electr.&Comput. Eng., Wayne State Univ., Detroit, MI
pp. 516-521

Online Task-Scheduling for Fault-Tolerant Low-Energy Real-Time Systems (Abstract)

P. Mishra , Dept. of ECE, Michigan Technol. Univ., Houghton, MI
null Tongquan Wei , Dept. of ECE, Michigan Technol. Univ., Houghton, MI
pp. 522-527

Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design (Abstract)

null Lei Wang , Dept. of Electr.&Comput. Eng., Connecticut Univ., Storrs, CT
null Shuo Wang , Dept. of Electr.&Comput. Eng., Connecticut Univ., Storrs, CT
pp. 535-540

System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems (Abstract)

D. Marculescu , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
S. Garg , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
pp. 541-546

A New RLC Buffer Insertion Algorithm (Abstract)

null Shiyan Hu , Texas A&M Univ., College Station, TX
null Jiang Hu , Texas A&M Univ., College Station, TX
null Zhanyuan Jiang , Texas A&M Univ., College Station, TX
pp. 553-557

Clock Buffer Polarity Assignment for Power Noise Reduction (Abstract)

G. Venkataraman , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
R. Samanta , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Jiang Hu , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 558-562

Combinatorial Algorithms for Fast Clock Mesh Optimization (Abstract)

G. Venkataraman , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Zhuo Feng , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Jiang Hu , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Peng Li , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 563-567

An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implications for Power Estimation and Hot-Spot Management (Abstract)

K. Banerjee , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
null Sheng-Chih Lin , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
pp. 568-574

Leakage Power Dependent Temperature Estimation to Predict Thermal Runaway in FinFET Circuits (Abstract)

A. Bansal , Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
M. Meterelliyoz , Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
null Jung Hwan Choi , Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
pp. 583-586

Runtime Distribution-Aware Dynamic Voltage Scaling (Abstract)

null Soo-Kwan Eo , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
null Jeong-Taek Kong , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
null Kyu-Myung Choi , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
null Hoonsang Jin , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
null Sungjoo Yoo , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
null Sungpack Hong , Syst. LSI Div., Samsung Electronics. Co. Ltd., Seoul
pp. 587-594

Formal Model of Data Reuse Analysis for Hierarchical Memory Organizations (Abstract)

F. Balasa , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
I.I. Luican , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
null Hongwei Zhu , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
pp. 595-600

An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems (Abstract)

null Chin-Hsien Wu , Dept. of Comput. Sci.&Inf. Eng., Nat. Taiwan Univ., Taipei
pp. 601-606

Design and Integration Methods for a Multi-threaded Dual Core 65nm Xeon? Processor (Abstract)

R. Varada , Intel Corp., Santa Clara, CA
J. Guzzo , Intel Corp., Santa Clara, CA
K. Chou , Intel Corp., Santa Clara, CA
M. Sriram , Intel Corp., Santa Clara, CA
pp. 607-610

Counterflow Pipelining: Architectural Support for Preemption in Asynchronous Systems using Anti-Tokens (Abstract)

M. Ampalam , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC
M. Singh , Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC
pp. 611-618

A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation (Abstract)

S. Ghosh , Sch. of Electr.&Comput. Eng., Purdue Univ., West Lafayette, IN
pp. 619-624

Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration (Abstract)

null Ting-Chi Wang , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
null Kuang-Yao Lee , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
pp. 633-640

Post-Placement Voltage Island Generation (Abstract)

R.L.S. Ching , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong
E.F.Y. Young , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong
K.C.K. Leung , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong
pp. 641-646

Prospects for Emerging Nanoelectronics in Mainstream Information Processing Systems (Abstract)

J. Bokor , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA
pp. 647-648

Carbon Nanotubes for Potential Electronic and Optoelectronic Applications (Abstract)

null Jia Chen , IBM TJ Watson Res. Center, Yorktown Heights, NY
pp. 649-650

Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization (Abstract)

T. Krishnamohan , Center for Integrated Syst., Stanford Univ., CA
null Arash , Center for Integrated Syst., Stanford Univ., CA
H.-S.P. Wong , Center for Integrated Syst., Stanford Univ., CA
null Jie Deng , Center for Integrated Syst., Stanford Univ., CA
null Hazeghi , Center for Integrated Syst., Stanford Univ., CA
G.C. Wan , Center for Integrated Syst., Stanford Univ., CA
pp. 651-654

Fill for Shallow Trench Isolation CMP (Abstract)

A.B. Kahng , Blaze DFM Inc., Sunnyvale, CA
pp. 661-668

An Optimal Simultaneous Diode/Jumper Insertion Algorithm for Antenna Fixing (Abstract)

null Zhe-Wei Jiang , Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei
pp. 669-674

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure (Abstract)

H. Mrabet , Univ. Pierre et Marie Curie, Paris
H. Mehrez , Univ. Pierre et Marie Curie, Paris
P. Souillot , Univ. Pierre et Marie Curie, Paris
Z. Marrakchi , Univ. Pierre et Marie Curie, Paris
pp. 675-679

Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs (Abstract)

G. Lemieux , Dept. of Electr.&Comput. Eng., British Columbia Univ.
D. Leong , Dept. of Electr.&Comput. Eng., British Columbia Univ.
M. Tom , Dept. of Electr.&Comput. Eng., British Columbia Univ.
pp. 680-687

Studying a GALS FPGA Architecture Using a Parameterized Automatic Design Flow (Abstract)

R. Vemuri , Cincinnati Univ., OH
null Xin Jia , Cincinnati Univ., OH
pp. 688-693

Conjoining Soft-Core FPGA Processors (Abstract)

D. Sheldon , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 694-701

High-Level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor (Abstract)

T. Awashima , Syst. Devices Res. Labs., NEC Corp., Kawasaki
Y. Kato , Syst. Devices Res. Labs., NEC Corp., Kawasaki
T. Toi , Syst. Devices Res. Labs., NEC Corp., Kawasaki
N. Nakamura , Syst. Devices Res. Labs., NEC Corp., Kawasaki
K. Wakabayashi , Syst. Devices Res. Labs., NEC Corp., Kawasaki
pp. 702-708

Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture (Abstract)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA
null Wei Jiang , Dept. of Comput. Sci., California Univ., Los Angeles, CA
null Yiping Fan , Dept. of Comput. Sci., California Univ., Los Angeles, CA
pp. 709-715

A Code Refinement Methodology for Performance-Improved Synthesis from C (Abstract)

W. Najjar , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
F. Vahid , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
G. Stitt , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 716-723

Leveraging Protocol Knowledge in Slack Matching (Abstract)

G. Venkataramani , Carnegie Mellon Univ., Pittsburgh, PA
S.C. Goldstein , Carnegie Mellon Univ., Pittsburgh, PA
pp. 724-729

Application-Independent Defect-Tolerant Crossbar Nano-Architectures (Abstract)

M.B. Tahoori , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
pp. 730-734

Nanowire Addressing with Randomized-Contact Decoders (Abstract)

J.E. Savage , Dept. of Comput. Sci., Brown Univ., Providence, RI
E. Rachlin , Dept. of Comput. Sci., Brown Univ., Providence, RI
pp. 735-742

On the Use of Bloom Filters for Defect Maps in Nanocomputing (Abstract)

R. Kastner , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
null Wenrui Gong , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
null Gang Wang , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
pp. 743-746
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