2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC) (2015)
Nov. 4, 2015 to Nov. 6, 2015
We develop a simple hierarchical model for the performance analysis of compute clusters assembled from multi-core compute nodes connected by a (high-speed) network. The performance is described by the dimensionless speed-up and efficiency in dependence on important hardware and application parameters. The hardware parameters are the number of compute nodes and the bandwidth the network, together with the number of cores per node, the theoretical performance of each core and the bandwidth of the main memory. The application parameters are the total number of operations performed on a number of bytes and the total number of bytes communicated between the processing units. In order to exemplify our concept we apply it to the scalar product of vectors, matrix multiplication, Linpack and FFT. Our previous performance models are contained as special cases in the new more comprehensive approach.
Computational modeling, Mathematical model, Bandwidth, Analytical models, Hardware, Computers, Multicore processing
H. Kredel, H. G. Kruse and S. Richling, "A Hierarchical Model for the Analysis of Efficiency and Speed-Up of Multi-core Cluster-Computers," 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC), Krakow, Poland, 2016, pp. 207-215.