Issue No. 01 - January-March (1999 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/4434.749134
The Huge Microphone Array project began in February 1994 to design, construct, debug, and test a real-time 512-microphone array system and to develop algorithms for it. Analysis of known algorithms indicated that signal-processing performance of over 6 Gflops would be required, while the need for portability--fitting it into a small van--also set an upper limit to the power required. These tradeoffs and many others have led to a unique design in both hardware and software. This two-part article presents the full design and its justifications. The authors also discuss performance for a few important algorithms relative to usage of processing-capability, response latency, and difficulty of programming. The first article in the last issue described system planning and design, while this issue's follow-up article describes the system itself.
Harvey F. Silverman, James L. Flanagan, William R. Patterson III, "The Huge Microphone Array, Part 2", IEEE Concurrency (out of print), vol. 7, no. , pp. 32-47, January-March 1999, doi:10.1109/4434.749134