The Community for Technology Leaders
Green Image
Issue No. 01 - January/February (2018 vol. 38)
ISSN: 0272-1732
pp: 56-65
Enrico Mezzetti , Barcelona Supercomputing Center (BSC), Spain
Leonidas Kosmidis , Barcelona Supercomputing Center (BSC), Spain
Jaume Abella , Barcelona Supercomputing Center (BSC), Spain
Francisco J. Cazorla , Barcelona Supercomputing Center (BSC), Spain
As software continues to control more system-critical functions in cars, its timing is becoming an integral element in functional safety. Timing validation and verification (V&V) assesses softwares end-to-end timing measurements against given budgets. The advent of multicore processors with massive resource sharing reduces the significance of end-to-end execution times for timing V&V and requires reasoning on (worst-case) access delays on contention-prone hardware resources. While Performance Monitoring Units (PMU) support this finer-grained reasoning, their design has never been a prime consideration in high-performance processors - where automotive-chips PMU implementations descend from - since PMU does not directly affect performance or reliability. To meet PMUs instrumental importance for timing V&V, we advocate for PMUs in automotive chips that explicitly track activities related to worst-case (rather than average) softwares behavior, are recognized as an ISO-26262 mandatory high-integrity hardware service, and are accompanied with detailed documentation that enables their effective use to derive reliable timing estimates.
automotive electronics, electronic engineering computing

E. Mezzetti, L. Kosmidis, J. Abella and F. J. Cazorla, "High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V," in IEEE Micro, vol. 38, no. 1, pp. 56-65, 2018.
382 ms
(Ver 3.3 (11022016))