Issue No. 03 - May.-Jun. (2017 vol. 37)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2017.55
Yipeng Huang , Columbia University
Ning Guo , Columbia University
Mingoo Seok , Columbia University
Yannis Tsividis , Columbia University
Simha Sethumadhavan , Columbia University
Approaching the post-Moore's law era, researchers are looking for scalable ways to get useful computation from existing silicon technology. This article presents a programmable analog accelerator for solving systems of linear equations. The authors compensate for commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty applying it to different workloads. On the basis of a prototyped analog accelerator chip, they compare the analog solver's performance and energy consumption against an efficient digital algorithm running on a general-purpose processor. The analog accelerator approach is 10 times faster and provides 33 percent energy savings. Owing to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint, which limits scalability. The authors conclude that problem classes outside of systems of linear equations could hold more promise for analog acceleration.
Mathematical model, Linear algebra, Acceleration, Computer architecture, Hardware, Calibration, Iterative methods
Y. Huang, N. Guo, M. Seok, Y. Tsividis and S. Sethumadhavan, "Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study," in IEEE Micro, vol. 37, no. 3, pp. 30-38, 2017.