Issue No. 03 - May-June (2016 vol. 36)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2016.35
Kaisheng Ma , Pennsylvania State University
Xueqing Li , Pennsylvania State University
Karthik Swaminathan , IBM T.J. Watson Research Center
Yang Zheng , Pennsylvania State University
Shuangchen Li , University of California, Santa Barbara
Yongpan Liu , Tsinghua University
Yuan Xie , University of California, Santa Barbara
John Jack Sampson , Pennsylvania State University
Vijaykrishnan Narayanan , Pennsylvania State University
Nonvolatile processors (NVPs) have integrated nonvolatile memory to preserve task-intermediate on-chip state during power emergencies. NVPs hide data backup and restoration from the executing software to provide an execution mode that will always eventually complete the current task. NVPs are emerging as a promising solution for energy-harvesting scenarios, in which the available power supply is unstable and intermittent, because of their ability to ensure that even short periods of sufficient power, on the order of tens of instructions, will result in net forward progress. This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP. The authors propose a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses.
Nonvolatile memory, Radio frequency, Microarchitecture, Machine learning, Computer architecture, Object recognition, Energy harvesting
K. Ma et al., "Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power," in IEEE Micro, vol. 36, no. 3, pp. 72-83, 2016.