Issue No. 02 - Mar.-Apr. (2016 vol. 36)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2016.18
Sagheer Ahmad , Xilinx
Vamsi Boppana , Xilinx
Ilya Ganusov , Xilinx
Vinod Kathail , Xilinx
Vidya Rajagopalan , Xilinx
Ralph Wittig , Xilinx
This article presents the Zynq UltraScale+ MPSoC (multiprocessor system on chip), which builds on the Zynq-7000 family. Compared to the first-generation Zynq, MPSoC increases performance and power efficiency while significantly improving the integration level between the SoC and the field-programmable gate array (FPGA). It also further raises the programming abstraction with the introduction of a new heterogeneous system-wide compiler. At the hardware level, system-wide coherency and shared virtual memory bridge across the processor subsystem into the programmable logic array. The new SDSoC (software-designed SoC) environment combines the ARM compiler with a high-level synthesis technology-based FPGA compiler and a full-system optimizing compiler to target all elements of the heterogeneous SoC from a common program source.
Field programmable gate arrays, Random access memory, Safety, Real-time systems, Memory management, Streaming media, Software
S. Ahmad, V. Boppana, I. Ganusov, V. Kathail, V. Rajagopalan and R. Wittig, "A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform," in IEEE Micro, vol. 36, no. 2, pp. 48-62, 2016.