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Issue No.06 - Nov.-Dec. (2013 vol.33)
pp: 56-65
Jay Patel , MoSys
Jeff Kumala , MoSys
Ming Liu , MoSys
Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine family of integrated circuits provides a significant improvement in effective memory performance by using high-speed serial I/O's, many banks of memory, a low-latency, highly efficient protocol, and intelligence within the device. The first member of the family can perform 2 billion 72-bit reads per second or 1 billion read-modify-write operations per second.
Bandwidth, Memory management, Synchronization, Random access memory, Performance evaluation,semiconductor memories, integrated circuits, interfaces, memory technologies, multiple data stream architectures
Bendik Kleveland, Michael John Miller, Ronald B. David, Jay Patel, Rajesh Chopra, Dipak K. Sikdar, Jeff Kumala, Socrates D. Vamvakos, Mike Morrison, Ming Liu, Jayaprakash Balachandran, "An Intelligent RAM with Serial I/Os", IEEE Micro, vol.33, no. 6, pp. 56-65, Nov.-Dec. 2013, doi:10.1109/MM.2013.7
1. 72Mb SigmaQuad-IIIe datasheet, no. GS8673EQ36BK-675, GSI Technology, 2011.
2. 72Mb QDR-II+ Xtreme SRAM datasheet, no. CY7C2564XV18, Cypress Semiconductor, 2012.
3. 576Mb RLDRAM 3 datasheet, no. MT44K16M36, Micron Technology, 2011.
4. B. Lynch and S. Kumar, “Smart Memory for High Performance Network Packet Forwarding,” Symp. High Performance Chips (Hot Chips 22), IEEE, 2010.
5. C. Hermsmeyer etal., “Towards 100G Packet Processing: Challenges and Technologies,” Bell Labs Tech. J., vol. 14, no. 2, 2009, pp. 57-79.
6. T. Sekiguchi etal., “1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing,” IEEE J. Solid State Circuits, vol. 46, no. 4, 2011, pp. 828-837.
7. M. Taouil and S. Hamdioui, “Yield Improvement for 3D Wafer-to-Wafer Stacked Memories,” J. Electronic Testing: Theory and Applications, vol. 28, no. 4, 2012, pp. 523-534.
8. “SSCS DL Betty Prince Talks to SSCS-Dallas on ‘Future Trends in Embedded DRAM Technology,’” IEEE Solid-State Circuits Mag., vol. 4, no. 1, 2012, pp. 36-40.
9. R. Kalla etal., “Power7: IBM's Next-Generation Server Processor,” IEEE Micro, vol. 30, no. 2, 2010, pp. 7-15.
10. G. Boyd etal., Common Electrical I/O (CEI)—Electrical and Jitter Interoperability Agreements for 6G+ bps and 11G+ bps I/O, no. OIF-CEI-02.0, Optical Internetworking Forum, 2005.
11. S. Vamvakos etal., “A 576 Mb DRAM with 16-channel 10.3125Gbps Serial I/O and 14.5ns Latency,” Proc. ESSCIRC, IEEE CS, 2012, pp. 458-461.
12. B. Holden, “Latency Comparison Between HyperTransport and PCI-Express in Communications Systems,” white paper, HyperTransport Consortium, 2006.
13. D. Patterson etal., “A Case for Intelligent RAM,” IEEE Micro, vol. 17, no. 2, 1997, pp.34-44.
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