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Issue No.04 - July-Aug. (2013 vol.33)
pp: 66-75
Youngtaek Kim , University of Texas at Austin
Lizy Kurian John , University of Texas at Austin
Sanjay Pant , Advanced Micro Devices
Srilatha Manne , Advanced Micro Devices
Michael Schulte , Advanced Micro Devices
W. Lloyd Bircher , Advanced Micro Devices
Madhu Saravana Sibi Govindan , Advanced Micro Devices
Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large voltage droops. This process is time-consuming and might need to be repeated several times to generate appropriate stressmarks for different system conditions (for example, different frequencies or di/dt throttling mechanisms). Furthermore, generating efficient di/dt stressmarks for multicore processors is difficult because of their complexity and synchronization issues. In this article, the authors measure and analyze di/dt issues on state-of-the-art multicore x86 systems. They present an automated di/dt stressmark generation framework called Audit to generate di/dt stressmarks quickly and effectively for multicore systems.
Fluctuations, Multicore processing, Voltage measurement, Voltage fluctuations, Resonant frequency, Instruction sets, Audit, reliability, voltage noise, di/dt, inductive noise, stressmark generation, voltage droop, power distribution network, low power, genetic algorithm, hardware measurement
Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael Schulte, W. Lloyd Bircher, Madhu Saravana Sibi Govindan, "Automating Stressmark Generation for Testing Processor Voltage Fluctuations", IEEE Micro, vol.33, no. 4, pp. 66-75, July-Aug. 2013, doi:10.1109/MM.2013.70
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