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Issue No. 04 - July-Aug. (2013 vol. 33)
ISSN: 0272-1732
pp: 46-55
Norbert Wehn , TU Kaiserslautern
Ulf Schlichtmann , TU München
Sani R. Nassif , IBM Research Austin
Andreas Herkersdorf , TU München
Christian Weis , TU Kaiserslautern
Christina Gimmler-Dumont , TU Kaiserslautern
Veit B. Kleeberger , TU München
ABSTRACT
Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliability problems purely at the technology level would cause prohibitive increases in power consumption. Thus, a cross-layer approach is required, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy. This article illustrates a methodology for dealing with scaling-related problems via two case studies that link models of low-level technology-related problems to system behavior.
INDEX TERMS
Resilience, Semiconductor devices, Performance evaluation, Data models, Robot sensing systems, Error analysis, design hierarchy, performance and reliability, semiconductor memories, computer architecture, scaled technologies, cross-layer approach, technology nodes
CITATION
Norbert Wehn, Ulf Schlichtmann, Sani R. Nassif, Daniel Mueller-Gritschneder, Andreas Herkersdorf, Christian Weis, Christina Gimmler-Dumont, Veit B. Kleeberger, "A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience", IEEE Micro, vol. 33, no. , pp. 46-55, July-Aug. 2013, doi:10.1109/MM.2013.67
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