The Community for Technology Leaders
RSS Icon
Issue No.04 - July-Aug. (2013 vol.33)
pp: 46-55
Veit B. Kleeberger , TU München
Christina Gimmler-Dumont , TU Kaiserslautern
Christian Weis , TU Kaiserslautern
Andreas Herkersdorf , TU München
Sani R. Nassif , IBM Research Austin
Ulf Schlichtmann , TU München
Norbert Wehn , TU Kaiserslautern
Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliability problems purely at the technology level would cause prohibitive increases in power consumption. Thus, a cross-layer approach is required, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy. This article illustrates a methodology for dealing with scaling-related problems via two case studies that link models of low-level technology-related problems to system behavior.
Resilience, Semiconductor devices, Performance evaluation, Data models, Robot sensing systems, Error analysis, design hierarchy, performance and reliability, semiconductor memories, computer architecture, scaled technologies, cross-layer approach, technology nodes
Veit B. Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn, "A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience", IEEE Micro, vol.33, no. 4, pp. 46-55, July-Aug. 2013, doi:10.1109/MM.2013.67
1. J. Cook and C. Zilles, "A Characterization of Instruction-Level Error Derating and Its Implications for Error Detection," IEEE Conf. Dependable Systems and Networks (DSN 08), IEEE CS, 2008, pp. 482-491.
2. M. Breuer, S. Gupta, and T. Mak, "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," IEEE Design & Test, vol. 21, no. 3, 2004, pp. 216-227.
3. A. Herkersdorf et al., "Cross-Layer Dependability Modeling and Abstraction in Systems on Chip," 9th Workshop Silicon Errors in Logic—System Effects, 2013.
4. D. Mueller-Gritschneder et al., "A Virtual Prototyping Platform for Real-Time Systems with a Case Study for a Two-Wheeled Robot," Proc. Conf. Design, Automation and Test in Europe (DATE 13), IEEE, 2013, pp. 1331-1334.
5. M. Zhang and N. Shanbhag, "Soft-Error-Rate-Analysis Methodology," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Oct. 2006, pp. 2140-2155.
6. S. Lee, S. Baeg, and P. Reviriego, "Memory Reliability Model for Accumulated and Clustered Soft Errors," IEEE Trans. Nuclear Science, Oct. 2011, pp. 2483-2492.
7. S. Mukherjee, Architecture Design for Soft Errors, Morgan Kaufmann, 2008.
8. B. Hochwald and S. Ten Brink, "Achieving Near-Capacity on a Multiple-Antenna Channel," IEEE Trans. Comm., Mar. 2003, pp. 389-399.
9. C. Gimmler-Dumont et al., "A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection," VLSI Design, Jan. 2012, article 2.
10. C. Gimmler-Dumont, C. Brehm, and N. Wehn, "Reliability Study on System Memories of an Iterative MIMO-BICM System," Proc. IEEE/IFIP 20th Int'l Conf. VLSI and System-on-Chip, IEEE, 2012, pp. 255-258.
11. I. Chang, D. Mohapatra, and K. Roy, "A Priority-Based 6t/8t Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications," IEEE. Trans. Circuits and Systems for Video Technology, Feb. 2011, pp. 101-112.
12. C. Brehm et al., "A Case Study on Error Resilient Architectures for Wireless Communication," Proc. 25th Int'l Conf. Architecture of Computing Systems (ARCS 12), Springer-Verlag, 2012, pp. 13-24.
37 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool