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Issue No.04 - July-Aug. (2013 vol.33)
pp: 35-45
Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. The authors present a mechanism that reduces excess voltage margin by introducing a critical-path monitor (CPM) circuit that measures available timing margin in real time; coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin; and adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. They first demonstrated this mechanism in an IBM Power7 server and proved its effectiveness in the Power7+ product. Power consumption on the VDD rail was reduced by 11 percent for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events.
Voltage control, Microprocessors, Frequency control, Program processors, Voltage measurement, Frequency measurement, Power7+, performance and reliability, measurement, performance, design, reliability, experimentation, timing margin, energy efficient, critical path, digital phase-lock loop, voltage speculation
Charles R. Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm S. Allen-Ware, Bishop Brock, Jose A. Tierno, John B. Carter, Robert W. Berry, "Active Guardband Management in Power7+ to Save Energy and Maintain Reliability", IEEE Micro, vol.33, no. 4, pp. 35-45, July-Aug. 2013, doi:10.1109/MM.2013.52
1. C. Lefurgy et al., "Active Management of Timing Guardband to Save Energy in POWER7," Proc. 44th Ann. Int'l Symp. Microarchitecture, ACM, 2011, pp. 1-11.
2. A. Drake et al., "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE, 2007, pp. 398-399.
3. M. Floyd et al., "Introducing the Adaptive Energy Management Features of the Power7 Chip," IEEE Micro, Mar./Apr. 2011, pp. 60-75.
4. J.A. Tierno, A.V. Rylyakov, and D.J. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI," IEEE J. Solid-State Circuits, Jan. 2008, pp. 42-51.
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