Issue No. 04 - July-Aug. (2013 vol. 33)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2013.71
Ulya R. Karpuzcu , University of Minnesota
Nam Sung Kim , University of Wisconsin-Madison
Josep Torrellas , University of Illinois at Urbana-Champaign
Near-threshold voltage computing (NTC) promises significant improvement in energy efficiency. Unfortunately, when compared to conventional, super-threshold voltage computing (STC), NTC is more sensitive to parametric variation. This results in not only slower and leakier cores, but also substantial speed and power differences between the cores in a many-core chip. NTC's potential cannot be unlocked without addressing the higher impact of variation. To confront variation at the architecture level, the authors introduce a parametric variation model for NTC. They then use the model to show the shortcomings of adapting state-of-the-art STC techniques for variation mitigation to NTC. Finally, they discuss how to tailor variation mitigation to NTC.
Energy efficiency, System-on-chip, Threshold voltage, Random access memory, Delays, Computational modeling, Power distribution, near-threshold voltage, multicores, energy and power efficiency, resilience, parameter variation
J. Torrellas, N. S. Kim and U. R. Karpuzcu, "Coping with Parametric Variation at Near-Threshold Voltages," in IEEE Micro, vol. 33, no. , pp. 6-14, 2013.