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Issue No.03 - May-June (2013 vol.33)
pp: 106-115
Mahdi Nazm Bojnordi , University of Rochester
Engin Ipek , University of Rochester
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable. Unfortunately, the stringent latency and throughput requirements of modern DDRx (double data rate memory interface technology) devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware. Pardis is the first programmable memory controller that can meet these challenges and thus satisfy the performance requirements of a high-speed DDRx interface.
Computer architecture, Memory management, Computer programs, Programming, Computer interfaces, double data rate memory interface technology, programmability, memory controllers, DDRx, Pardis
Mahdi Nazm Bojnordi, Engin Ipek, "Programmable DDRx Controllers", IEEE Micro, vol.33, no. 3, pp. 106-115, May-June 2013, doi:10.1109/MM.2013.29
1. J. Martin et al., "A Microprogrammable Memory Controller for High-Performance Dataflow Applications," Proc. 35th European Solid-State Circuits Conf. (ESSCIRC 09), IEEE, 2009, pp. 348-351.
2. G. Kornaros et al., "A Fully Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates," Proc. 40th Design Automation Conf. (DAC 03), ACM, 2003, pp. 54-59.
3. Micron Technology, "TN-29-01: Increasing NAND Flash Performance," 2006; Technical%20Note/NAND%20Flashtn2901.pdf .
4. J. Kuskin et al., "The Stanford FLASH Multiprocessor," Proc. 21st Int'l Symp. Computer Architecture (ISCA 94), IEEE CS, 1994, pp. 302-313.
5. S.K. Reinhardt, J.R. Larus, and D.A. Wood, "Tempest and Typhoon: User-level Shared Memory," Proc. 21st Int'l Symp. Computer Architecture (ISCA 94), IEEE CS, 1994, pp. 325-336.
6. J. Carter et al., "Impulse: Building a Smarter Memory Controller," Proc. 15th Int'l Symp. High-Performance Computer Architecture (HPCA 99), IEEE CS, 1999, pp. 70-79.
7. M. Browne et al., "Design Verification of the Cache Coherent Shared-Memory System," IEEE Trans. Computers, Jan. 1998, pp. 135-140.
8. A. Agarwal et al., "The MIT Alewife Machine: Architecture and Performance," Proc. 22nd Ann. Int'l Symp. Computer Architecture (ISCA 95), ACM, 1995, pp. 2-13.
9. A. Firoozshahian et al., "A Memory System Design Framework: Creating Smart Memories," Proc. 36th Int'l Symp. Computer Architecture (ISCA 09), ACM, 2009, pp. 406-417.
10. M.N. Bojnordi and E. Ipek, "PARDIS: A Programmable Memory Controller for the DDRx Interfacing Standards," Proc. 39th Int'l Symp. Computer Architecture (ISCA 12), IEEE, 2012, pp. 13-24.
11. S. Rixner et al., "Memory Access Scheduling," Proc. 27th Int'l Symp. Computer Architecture (ISCA 00), IEEE, 2000, pp. 128-138.
12. O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems," Proc. 35th Int'l Symp. Computer Architecture (ISCA 08), IEEE, 2008, pp. 32-41.
13. Y. Kim et al., "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior," Proc. 43rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE, 2010, pp. 65-76.
14. I. Hur and C. Lin, "A Comprehensive Approach to DRAM Power Management," Proc. Int'l Symp. High Performance Computer Architecture (HPCA 08), IEEE CS, 2008, pp. 305-316.
15. J. Stuecheli et al., "Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory," Proc. 43rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE, 2010, pp. 375-384.
16. J. Renau et al., "SESC Simulator," Jan. 2005; http:/
17. Z. Zhang, Z. Zhu, and X. Zhang, "A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality," Proc. 33rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, 2000, ACM, pp. 32-41.
18. JEDEC, DDR3 SDRAM Specification, 2010.
19. J. Jeddeloh and B. Keeth, "Hybrid Memory Cube New DRAM Architecture Increases Density and Performance," Proc. IEEE Symp. VLSI Technology, IEEE, 2012, pp. 87-88.
20. J. Carter et al., "Impulse: Building a Smarter Memory Controller," Proc. 5th Int'l Symp. High Performance Computer Architecture (HPCA 99), IEEE CS, 1999, pp. 70-79.
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