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Issue No. 03 - May-June (vol. 33)
ISSN: 0272-1732
From the Editor in Chief

Ten Years of Top Picks (HTML)

Erik R. Altman , Thomas J. Watson Research Center
pp. 2
Guest Editors' Introduction
Top Picks

Designing for Responsiveness with Computational Sprinting (Abstract)

Arun Raghavan , University of Pennsylvania
Yixin Luo , University of Michigan
Anuj Chandawalla , University of Michigan
Marios Papaefthymiou , University of Michigan
Kevin P. Pipe , University of Michigan
Thomas F. Wenisch , University of Michigan
Milo M.K. Martin , University of Pennsylvania
pp. 8-15

Neural Acceleration for General-Purpose Approximate Programs (Abstract)

Hadi Esmaeilzadeh , University of Washington
Adrian Sampson , University of Washington
Luis Ceze , University of Washington
Doug Burger , Microsoft Research
pp. 16-27

Scaling the Energy Proportionality Wall with KnightShift (Abstract)

Daniel Wong , University of Southern California
Murali Annavaram , University of Southern California
pp. 28-37

Hardware-Enforced Comprehensive Memory Safety (Abstract)

Santosh Nagarakatte , Rutgers University
Milo M.K. Martin , University of Pennsylvania
Steve Zdancewic , University of Pennsylvania
pp. 38-47

Inspection-Resistant Memory Architectures (Abstract)

Jonathan Kaveh Valamehr , University of California, Santa Barbara
Melissa Chase , Microsoft Research
Seny Kamara , Microsoft Research
Andrew Putnam , Microsoft Research
Daniel Shumow , Microsoft Research
Vinod Vaikuntanathan , University of Toronto
Timothy Sherwood , University of California, Santa Barbara
pp. 48-56

Relyzer: Application Resiliency Analyzer for Transient Faults (Abstract)

Siva Kumar Sastry Hari , University of Illinois at Urbana-Champaign
Sarita V. Adve , University of Illinois at Urbana-Champaign
Helia Naeimi , Intel
pp. 58-66

A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security (Abstract)

John Demme , Columbia University
Robert Martin , Columbia University
Adam Waksman , Columbia University
Simha Sethumadhavan , Columbia University
pp. 68-77

Cache-Conscious Thread Scheduling for Massively Multithreaded Processors (Abstract)

Timothy G. Rogers , University of British Columbia
Mike O'Connor , AMD Research
Tor M. Aamodt , University of British Columbia
pp. 78-85

Parallel Block Vectors: Collection, Analysis, and Uses (Abstract)

Melanie Kambadur , Columbia University
Kui Tang , Columbia University
Martha A. Kim , Columbia University
pp. 86-94

A Safety-First Approach to Memory Models (Abstract)

Abhayendra Singh , University of Michigan
Satish Narayanasamy , University of Michigan
Daniel Marino , Symantec Research Labs
Todd Millstein , University of California
Madanlal Musuvathi , Microsoft Research
pp. 96-104

Programmable DDRx Controllers (Abstract)

Mahdi Nazm Bojnordi , University of Rochester
Engin Ipek , University of Rochester
pp. 106-115
Micro Review
Micro Economics

Differentiated Platforms (Abstract)

Shane Greenstein , Kellogg School of Management
pp. 120
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