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Issue No. 06 - Nov.-Dec. (2012 vol. 32)
ISSN: 0272-1732
pp: 28-37
David May , XMOS
The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications, and I/O are supported by the instruction set of the XCore processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
Instruction sets, Computer architecture, Programming, Registers, Real-time systems, Multithreading, multichip, XMOS architecture, multithreaded processor, XCore processor, XMOS interconnect, energy efficiency, multicore

D. May, "The XMOS Architecture and XS1 Chips," in IEEE Micro, vol. 32, no. , pp. 28-37, 2012.
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