Issue No. 05 - Sept.-Oct. (2012 vol. 32)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2012.51
Venkatraman Govindaraju , University of Wisconsin–Madison
Chen-Han Ho , University of Wisconsin–Madison
Tony Nowatzki , University of Wisconsin–Madison
Jatin Chhugani , Intel
Nadathur Satish , Intel
Karthikeyan Sankaralingam , University of Wisconsin–Madison
Changkyu Kim , Intel
The DySER (Dynamically Specializing Execution Resources) architecture supports both functionality specialization and parallelism specialization. By dynamically specializing frequently executing regions and applying parallelism mechanisms, DySER provides efficient functionality and parallelism specialization. It outperforms an out-of-order CPU, Streaming SIMD Extensions (SSE) acceleration, and GPU acceleration while consuming less energy. The full-system field-programmable gate array (FPGA) prototype of DySER integrated into OpenSparc demonstrates a practical implementation.
Parallel processing, Computer architecture, Hardware, Energy efficiency, Field programmable gate arrays, Prototypes, DySER, architecture, specialization, data-level parallelism, accelerator, energy efficiency
C. Kim et al., "DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing," in IEEE Micro, vol. 32, no. , pp. 38-51, 2012.