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Issue No.03 - May/June (2012 vol.32)
pp: 122-134
Hadi Esmaeilzadeh , University of Washington
Emily Blem , University of Wisconsin—Madison
Renee St. Amant , University of Texas at Austin
Karthikeyan Sankaralingam , University of Wisconsin—Madison
Doug Burger , Microsoft Research
A key question for the microprocessor research and design community is whether scaling multicores will provide the performance and value needed to scale down many more technology generations. To provide a quantitative answer to this question, a comprehensive study that projects the speedup potential of future multicores and examines the underutilization of integration capacity—dark silicon—is timely and crucial.
dark silicon, modeling, power, technology scaling, multicore, Moore's law
Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, Doug Burger, "Dark Silicon and the End of Multicore Scaling", IEEE Micro, vol.32, no. 3, pp. 122-134, May/June 2012, doi:10.1109/MM.2012.17
1. G.E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, no. 8, 1965, pp. 56-59.
2. R.H. Dennard et al., "Design of Ion-Implanted Mosfet's with Very Small Physical Dimensions," IEEE J. Solid-State Circuits, vol. 9, no. 5, 1974, pp. 256-268.
3. S. Borkar, "The Exascale Challenge," Proc. Int'l Symp. on VLSI Design, Automation and Test (VLSI-DAT 10), IEEE CS, 2010, pp. 2-3.
4. F. Pollack, "New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies," Proc. 32nd Ann. ACM/IEEE Int'l Symp. Microarchitecture (Micro 99), IEEE CS, 2009, p. 2.
5. Z. Guz et al., "Many-Core vs. Many-Thread Machines: Stay Away From the Valley," IEEE Computer Architecture Letters, vol. 8, no. 1, 2009, pp. 25-28.
6. G.M. Amdahl, "Validity of the Single Processor Approach to Achieving Large-scale Computing Capabilities," Proc. Joint Computer Conf. American Federation of Information Processing Societies (AFIPS 67), ACM, 1967, doi:10.1145/1465482.1465560.
7. M. Bhadauria, V. Weaver, and S. McKee, "Understanding PARSEC Performance on Contemporary CMPs," Proc. IEEE Int'l Symp. Workload Characterization (IISWC 09), IEEE CS, 2009, pp. 98-107.
8. C. Bienia et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," Proc. 17th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 08), ACM, 2008, pp. 72-81.
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