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New Blood, Cool Chips, and Heterogeneous Designs

Erik R. , ealtman@us.ibm.com

Pages: pp. 2-3

Abstract—This column discusses cool chips, and their place in the history of computing and current heterogeneous systems. This column also introduces the new Editorial Board members.

Keywords—cool chips, heterogeneous computing, GPU, DSP, history of computing, IEEE Micro editorial board members


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With this issue, I have the honor of welcoming five new members to the IEEE Micro Editorial Board: Lieven Eeckhout, R. Govindarajan, Toshio Nakatani, André Seznec, and Olivier Temam. As the accompanying sidebar indicates, each of these distinguished leaders in our community brings new perspectives and experience, and will help make IEEE Micro an even better and more compelling magazine. I am delighted and thankful that they accepted my invitation to join the Board.

This issue focuses on cool chips, and I thank Guest Editors Makoto Ikeda and Fumio Arakawa for their fine job. The types of chips and domains include networking, imaging, software radio, and reconfigurable arrays of processing elements. The microarchitectural heterogeneity in this issue continues a theme from both our last issue on CPUs vs. GPUs and our July/August issue on Big Chips, whose size helps enable heterogeneity. This increased heterogeneity is visible in legacy computing platforms and even more so in new (and "cool") computing platforms, like cell phones and tablets, which will probably accelerate the heterogeneous trend as they become more of a driving force in "general purpose" design.

This heterogeneity in turn raises larger questions, a number of which are explored in this issue. For example, where should activities such as software-defined radio be done, and who decides—the microarchitecture, a hypervisor, or a high-level piece of management software? Is it more efficient and quicker to compute on a mobile device or on a server in a cloud to which the mobile device has access? Amazon's recently introduced Kindle Fire explicitly raises these questions.

For microarchitects, these issues could imply increased collaboration with others, as traditional microarchitectural issues such as power management expand to include new nonmicroarchitectural options. These options in turn raise questions such as how information should be exchanged between all the components participating in power management. For example, if multiple activities need to be performed simultaneously, which activities are best done locally, and which are best offloaded? Making such a decision well probably requires both microarchitectural and software activity and exchange of information between the two.

Of course, such decisions are not limited to remote offload. Is a computation better performed in a CPU or a GPU or a DSP? Currently, such decisions are made statically as designs are partitioned. However, fat binaries could emerge, which allow a function to execute on multiple computing engines within a single platform, leaving it to some form of platform microarchitecture to determine the best option.

This heterogeneity raises other issues. Until recently, mainstream computing platforms have generally run at frequencies within a small multiple of each other, such as 1 to 5 GHz. However, such narrow ranges have not always been the case. When the IBM PC debuted 30 years ago, it ran at 4.77 MHz versus 80 MHz for a Cray-1A, a difference of more than 16×. Heterogeneous designs might be pushing us back to such an era, which would have implications not only on microarchitecture, but on software and the performance portability of software from one platform to another.

Other areas will also be impacted. The last several years have seen great focus on virtualization, especially in support of cloud computing. However, heterogeneity makes virtualization significantly more challenging and could provide a counterweight to the virtualization trend. Heterogeneity is also making for interesting tensions and interactions between shared memory and cache consistency on the one hand and on-chip networks on the other.

All in all, the impact and variety of microarchitecture has never been so great, nor has the long-term outcome been so unclear. We live in interesting times.

Erik R. Altman

Editor in Chief

IEEE Micro

IEEE Micro Editorial Board News

IEEE Micro welcomes five new members to its editorial board.

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Lieven Eeckhout is an associate professor at Ghent University. His research interests include computer architecture and the hardware/software interface in general, and performance modeling and analysis, simulation methodology, and workload characterization in particular. Eeckhout has a PhD in computer science and engineering from Ghent University. He was the program chair for the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), and the general chair for ISPASS 2010. He received two IEEE Micro Top Picks Awards and recently wrote a synthesis lecture on "Computer Architecture Performance Evaluation Methods" published by Morgan and Claypool. He graduated seven PhD students, and currently supervises four postdoctoral researchers and eight PhD students. He participates in the ExaScience Lab, part of Intel Labs Europe, focusing on architectural simulation techniques for exascale systems, and he was recently awarded an ERC Starting Independent Researcher Grant.

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R. Govindarajan is a professor of the Supercomputer Education and Research Centre and the Department of Computer Science and Automation at the Indian Institute of Science. His research interests include computer architecture, compiler analysis and optimizations, and high-performance computing. Govindarajan has a PhD in computer science from the Indian Institute of Science. He has held postdoctoral research positions at the University of Western Ontario and McGill University, and a faculty position in the Department of Computer Science at the Memorial University of Newfoundland. He has held visiting faculty positions at the University of Delaware and Arizona State University. He has more than 100 publications in international journals and refereed international conference proceedings. He is a senior member of IEEE and a member of the IEEE Computer Society.

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Toshio Nakatani is an IBM Distinguished Engineer and a senior manager of systems at IBM Research's Tokyo Research Laboratory, where he has led various advanced compiler projects, including the industry-leading IBM Java JIT compilers. His research interests include computer architectures, optimizing compilers, and algorithms for parallel computer systems. Nakatani has a PhD in computer science from Princeton University. He was named an ACM Distinguished Engineer in 2007 and received an IBM Corporate Award in 2000. He was a program committee member of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT 2011), the International Conference on Supercomputing (ICS 2010), and the 3rd Annual Haifa Experimental Systems Conference (SYSTOR 2010).

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André Seznec is a senior research director at INRIA Rennes, where he leads the ALF (Amdahl's Law is Forever) project team. He has focused his research on processor architecture since beginning his PhD thesis. Seznec has a Doctorat ès Sciences in computer science from the University of Rennes I in 1987. He led the CAPS (Compiler Parallel Architecture and Systems) project team at INRIA Rennes from 1994 to 2008. He spent a sabbatical year with the VSSAD, Alpha Development Group at Compaq from 1999 to 2000. Seznec has published more than 70 papers in major computer architecture conferences and journals, including 13 papers at the IEEE International Symposium on Computer Architecture (ISCA). He has supervised 15 PhD students. Seznec has been particularly active in the cache architecture field, branch prediction, and memory architecture.

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Olivier Temam is a senior research fellow at INRIA, where he leads the ByMoore group (BeYond MOORE), which focuses on alternative computing architectures, such as defect-tolerant accelerators. He was a full professor at the University of Paris Sud before joining INRIA. He is also an adjunct professor at École Polytechnique in France. He has been in the field for nearly two decades, and his research has spanned architecture, compilers, parallelization, simulation, and more. He has served multiple times on the program committees of ISCA and MICRO. In 2010, he gave a keynote at ISCA. In 2011, he was the general chair of the International Symposium on Code Generation and Optimization (CGO), and a program chair of the International Conference on High Performance Embedded Architectures and Compilers (HiPEAC).

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