The Community for Technology Leaders
Green Image
Issue No. 04 - July/August (2011 vol. 31)
ISSN: 0272-1732
pp: 51-62
David Papa , Broadway Technology
Cliff Sze , IBM Austin Research Laboratory
Zhuo Li , IBM Austin Research Laboratory
Gi-Joon Nam , IBM Austin Research Laboratory
Charles Alpert , IBM Austin Research Laboratory
Igor L. Markov , University of Michigan, Ann Arbor
<p>In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.</p>
physical synthesis, systems on chips

D. Papa et al., "Physical Synthesis with Clock-Network Optimization for Large Systems on Chips," in IEEE Micro, vol. 31, no. , pp. 51-62, 2011.
95 ms
(Ver 3.3 (11022016))