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Issue No. 04 - July/August (2011 vol. 31)
ISSN: 0272-1732
pp: 30-41
Sanjay J. Patel , University of Illinois at Urbana-Champaign
Steven S. Lumetta , University of Illinois at Urbana-Champaign
Matthew R. Johnson , University of Illinois at Urbana-Champaign
Daniel R. Johnson , University of Illinois at Urbana-Champaign
John H. Kelm , University of Illinois at Urbana-Champaign
William Tuohy , University of Illinois at Urbana-Champaign
ABSTRACT
<p>Rigel is a single-chip accelerator architecture with 1,024 independent processing cores targeted at a broad class of data- and task-parallel computation. This article discusses Rigel's motivation, evaluates its performance scalability as well as power and area requirements, and explores memory systems in the context of 1,024-core single-chip accelerators. The authors also consider future opportunities and challenges for large-scale designs.</p>
INDEX TERMS
Multiple data-stream architectures (multiprocessors), multiple instruction, multiple data processors, parallel processors, parallel architectures, multicore, single-chip multiprocessors
CITATION
Sanjay J. Patel, Steven S. Lumetta, Matthew R. Johnson, Daniel R. Johnson, John H. Kelm, William Tuohy, "Rigel: A 1,024-Core Single-Chip Accelerator Architecture", IEEE Micro, vol. 31, no. , pp. 30-41, July/August 2011, doi:10.1109/MM.2011.40
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