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Issue No.04 - July/August (2011 vol.31)
pp: 16-29
Wei Huang , IBM Research - Austin
Karthick Rajamani , IBM Research - Austin
Mircea R. Stan , University of Virginia
Kevin Skadron , University of Virginia
<p>The past few years have witnessed high-end processors with increasing numbers of cores and larger dies. With limited instruction-level parallelism, chip power constraints, and technology-scaling limitations, designers have embraced multiple cores rather than single-core performance scaling to improve chip throughput. This article examines whether this approach is sustainable by scaling from a state-of-the-art big-chip design point using analytical models.</p>
big chips, technology scaling, many-core processor, power, temperature, area, design constraints, cooling solution, processor architecture, system architecture
Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron, "Scaling with Design Constraints: Predicting the Future of Big Chips", IEEE Micro, vol.31, no. 4, pp. 16-29, July/August 2011, doi:10.1109/MM.2011.42
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