The Community for Technology Leaders
RSS Icon
Issue No.02 - March/April (2011 vol.31)
pp: 26-40
<p>The zEnterprise 196 is the latest IBM System zSeries mainframe computer, which builds on IBM's 46-year heritage of compatible enterprise-class machines. This design advances the prior z10 processor pipeline with out- of-order execution to achieve considerable performance gains in legacy online transaction processing and computationally intensive workloads. This article describes the system structure and details of this new high-frequency microprocessor.</p>
zEnterprise 196, z196, mainframe computer, high-frequency microprocessor, zSeries, transaction processing, hardware
Brian W. Curran, Lee E. Eisen, Eric M. Schwarz, Pak-kin Mak, James Warnock, Patrick J. Meaney, Michael Fee, "The zEnterprise 196 System and Microprocessor", IEEE Micro, vol.31, no. 2, pp. 26-40, March/April 2011, doi:10.1109/MM.2011.34
1. C.F. Webb, "IBM z10: The Next-Generation Mainframe Microprocessor," IEEE Micro, vol. 28, no. 2, 2008, pp. 19-29.
2. J.M. Tendler et al., "POWER4 System Microarchitecture," IBM J. Research and Development, vol. 46, no. 1, 2002, pp. 5-25.
3. C.N. Keltcher et al., "The AMD Opteron Processor for Multiprocessor Servers," IEEE Micro, vol. 23, no. 2, 2003, pp. 66-76.
4. z/Architecture: Principles of Operation, IBM, order no. SA22-7832-07, Aug. 2010; dz9zr008.pdf.
5. S. Narasimha et al., "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography," Proc. Int'l Electron Devices Meeting (IEDM 06), IEEE Press, 2006, doi:10.1109/IEDM.2006.346879.
6. J. Warnock et al, "POWER7 Local Clocking and Clocked Storage Elements," Proc. Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 178-179.
7. D. Wendel et al., "The Implementation of POWER7: A Highly Parallel and Scalable Multi-core High-End Server Processor," Proc. Int'l Solid-State Circuits Conf. (ISSCC 10), IEEE Press, 2010, pp. 102-103.
8. G. Northrop et al., "A Semi-custom Design Flow in High-Performance Microprocessor Design," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 426-431.
9. R. Berridge et al., "IBM POWER6 Microprocessor Physical Design and Design Methodology," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 685-714.
10. R. Puri, "Will 22nm Be Our Catch 22! Design and CAD Challenges," Proc. Int'l Symp. Physical Design (ISPD 09), ACM Press, 2009, pp. 59-60.
11. Y.-H. Chan et al., "Physical Synthesis Methodology for High Performance Microprocessors," Proc. 40th Design Automation Conf. (DAC 03), ACM Press, 2003, pp. 696-701.
12. C. Visweswariah, "Death, Taxes and Failing Chips," Proc. 40th Design Automation Conf. (DAC 03), ACM Press, 2003, pp. 343-347.
13. L.A. Lastras-Montaño et al., "A New Class of Array Codes for Memory Storage," Proc. Information Theory and Applications Workshop, Univ. of California, San Diego, 2011; paper_1895.pdf.
40 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool