Issue No. 01 - January/February (2011 vol. 31)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2010.99
Bogdan F. Romanescu , Duke University
Alvin R. Lebeck , Duke University
Daniel J. Sorin , Duke University
<p>Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.</p>
Memory consistency, virtual memory, address translation, dynamic verification
B. F. Romanescu, D. J. Sorin and A. R. Lebeck, "Address Translation Aware Memory Consistency," in IEEE Micro, vol. 31, no. , pp. 109-118, 2010.