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Issue No. 01 - January/February (2011 vol. 31)
ISSN: 0272-1732
pp: 90-98
Jeffrey Stuecheli , University of Texas at Austin
Dimitris Kaseridis , University of Texas at Austin
Lizy K. John , University of Texas at Austin
David Daly , IBM Thomas J. Watson Research Center
Hillery C. Hunter , IBM Thomas J. Watson Research Center
ABSTRACT
<p>To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance.</p>
INDEX TERMS
Memory, DRAM, cache, memory bandwidth, cache write-back, memory scheduling, last-level cache, cache replacement, DRAM page-mode, DRAM parameters
CITATION

H. C. Hunter, D. Kaseridis, J. Stuecheli, D. Daly and L. K. John, "Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue," in IEEE Micro, vol. 31, no. , pp. 90-98, 2010.
doi:10.1109/MM.2010.102
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