The Community for Technology Leaders
RSS Icon
Issue No.01 - January/February (2011 vol.31)
pp: 65-77
Matthew A. Watkins , Harvey Mudd College
David H. Albonesi , Cornell University
<p>ReMAP is a reconfigurable architecture for accelerating and parallelizing applications within a heterogeneous chip multiprocessor (CMP). Clusters of cores share a common reconfigurable fabric adaptable for individual thread computation or fine-grained communication with integrated computation. ReMAP demonstrates significantly higher performance and energy efficiency than hard-wired communication-only mechanisms, and over allocating the fabric area to additional or more powerful cores.</p>
ReMAP, chip multiprocessors, specialized programmable logic, reconfigurable architecture, fine-grained communication
Matthew A. Watkins, David H. Albonesi, "ReMAP: A Reconfigurable Architecture for Chip Multiprocessors", IEEE Micro, vol.31, no. 1, pp. 65-77, January/February 2011, doi:10.1109/MM.2011.14
1. M.A. Watkins and D.H. Albonesi, "Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors," Proc. 19th IEEE/ACM Int'l Conf. Parallel Architectures and Compilation Techniques, ACM Press, 2010, pp. 41-52.
2. M.A. Watkins, M. Cianchetti, and D.H. Albonesi, "Shared Reconfigurable Architectures for CMPs," Proc. 18th Int'l Conf. Field-Programmable Logic and Applications, IEEE Press, 2008, pp. 299-304.
3. C.J. Beckmann and C.D. Polychronopoulos, "Fast Barrier Synchronization Hardware," Proc. 1990 ACM/IEEE Conf. Supercomputing, IEEE CS Press, 1990, pp. 180-189.
4. J. Sampson et al., "Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers," Proc. IEEE/ACM 39th Ann. Int'l Symp. Microarchitecture, IEEE CS Press, 2006, pp. 235-246.
5. M.A. Watkins and D.H. Albonesi, "ReMAP: A Reconfigurable Heterogeneous Multicore Architecture," Proc. 43rd Ann. IEEE/ACM Int'l Symp. Microarchitecture, ACM Press, 2010, pp. 497-508.
6. E. Caspi et al., "Stream Computations Organized for Reconfigurable Execution," Proc. Roadmap to Reconfigurable Computing, 10th Int'l Workshop Field-Programmable Logic and Applications, Springer, 2000, pp. 605-614.
7. R. Rangan et al., "Decoupled Software Pipelining with the Synchronization Array," Proc. 13th IEEE/ACM Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2004, pp. 177-188.
8. J.S. Emer, "An Evolution of General Purpose Processing: Reconfigurable Logic Computing," Proc. 7th Ann. IEEE/ACM Int'l Symp. Code Generation and Optimization, IEEE CS Press, 2009, doi:10.1109/CGO.2009.38.
9. M. Feldman, "Reconfigurable Computing Prospects on the Rise," HPCwire,3 Dec. 2008; .
22 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool