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Issue No.01 - January/February (2011 vol.31)
pp: 11-19
Doe Hyun Yoon , The University of Texas at Austin
Mattan Erez , The University of Texas at Austin
<p>Virtualized error checking and correcting (ECC) is a scheme that virtualizes memory-error correction. Unlike traditional uniform ECC, which provides a fixed level of error tolerance, virtualized ECC enables flexible memory protection by mapping redundant information needed for correcting errors onto the memory namespace. Additionally, virtualized ECC enables error-correction mechanisms that can adapt to user and system demands.</p>
Error correction, fault tolerance, memory systems, reliability, error checking and correcting, ECC
Doe Hyun Yoon, Mattan Erez, "Virtualized ECC: Flexible Reliability in Main Memory", IEEE Micro, vol.31, no. 1, pp. 11-19, January/February 2011, doi:10.1109/MM.2010.103
1. B. Schroeder, E. Pinheiro, and W.D. Weber, "DRAM Errors in the Wild: A Large-Scale Field Study," Proc. 11th Int'l Joint Conf. Measurement and Modeling of Computer Systems (Sigmetrics 09), ACM, 2009, pp. 193-204.
2. T.J. Dell, "A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory," IBM Microelectronics Division, Nov. 1997.
3. J.H. Ahn et al., "Future Scaling of Processor-Memory Interfaces," Proc. Int'l Conf. High Performance Computing, Networking, Storage and Analysis (SC 09), ACM, 2009, doi:10.1145/1654059.1654102.
4. S. Ankireddi and T. Chen, "Challenges in Thermal Management of Memory Modules," Feb. 2008, .
5. P.M. Wells, K. Chakraborty, and G.S. Sohi, "Mixed-Mode Multicore Reliability," Proc. 14th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 09), ACM, 2009, pp. 169-180.
6. D.H. Yoon and M. Erez, "Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches," Proc. 36th Int'l Symp. Computer Architecture (ISCA 09), ACM, 2009, pp. 116-127.
7. C. Slayman, "Impact of Error Correction Code and Dynamic Memory Reconfiguration on High-Reliability/Low-Cost Server Memory," Proc. IEEE Int'l Integrated Reliability Workshop (IIRW 06), IEEE Press, 2006, pp. 190-193.
8. C.L. Chen and M.Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," IBM J. Research and Development, vol. 28, no. 2, 1984, pp. 124-134.
9. I.S. Reed and G. Solomon, "Polynomial Codes over Certain Finite Fields," J. Soc. Industrial and Applied Math, vol. 8, no. 2, 1960, pp. 300-304.
10. D.H. Yoon and M. Erez, "Virtualized and Flexible ECC for Main Memory," Proc. 15th Int'l. Conf. Architectural Support for Programming Language and Operating Systems (ASPLOS 10), ACM Press, 2010, pp. 397-408.
11. A.N. Udipi et al., "Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores," Proc. 37th Ann. Int'l Symp. Computer Architecture (ISCA 10), ACM Press, 2010, pp. 175-186.
12. "CCC Visioning Study on Cross-Layer Reliability," Mar. 2010, http:/
13. NVIDIA, "Next Generation CUDA Architecture," .
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