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TABLE OF CONTENTS
Issue No. 01 - January/February (vol. 31)
ISSN: 0272-1732
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pp. 1
From the Editor in Chief

A Solid Past, A Vital Future (HTML)

Erik R. Altman , ealtman@us.ibm.com
pp. 4-5
Guest Editors' Introduction: Top Picks

Top Picks (HTML)

Onur Mutlu , Carnegie Mellon University
Yale N. Patt , University of Texas at Austin
pp. 6-10
Top Picks

Virtualized ECC: Flexible Reliability in Main Memory (Abstract)

Mattan Erez , The University of Texas at Austin
Doe Hyun Yoon , The University of Texas at Austin
pp. 11-19

Voltage Noise in Production Processors (Abstract)

Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
Simone Campanoni , Harvard University
Svilen Kanev , Harvard University
Michael D. Smith , Harvard University
Wonyoung Kim , Harvard University
Vijay Janapa Reddi , Harvard University
pp. 20-28

Aérgia: A Network-on-Chip Exploiting Packet Latency Slack (Abstract)

Onur Mutlu , Carnegie Mellon University
Thomas Moscibroda , Microsoft Research
Chita R. Das , Pennsylvania State University
Reetuparna Das , Pennsylvania State University
pp. 29-41

Cohesion: An Adaptive Hybrid Memory Model for Accelerators (Abstract)

Steven S. Lumetta , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
John H. Kelm , University of Illinois at Urbana-Champaign
Daniel R. Johnson , University of Illinois at Urbana-Champaign
William Tuohy , University of Illinois at Urbana-Champaign
pp. 42-55

Data Marshaling for Multicore Systems (Abstract)

Onur Mutlu , Carnegie Mellon University
Yale Patt , The University of Texas at Austin, Austin
M. Aater Suleman , University of Texas at Austin
Jose A. Joao , University of Texas at Austin
Khubaib Khubaib , University of Texas at Austin
Yale N. Patt , University of Texas at Austin
pp. 56-64

Thread Cluster Memory Scheduling (Abstract)

Onur Mutlu , Carnegie Mellon University
Michael Papamichael , Carnegie Mellon University
Yoongu Kim , Carnegie Mellon University
Mor Harchol-Balter , Carnegie Mellon University
pp. 78-89

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue (Abstract)

Hillery C. Hunter , IBM Thomas J. Watson Research Center
Dimitris Kaseridis , University of Texas at Austin
Jeffrey Stuecheli , University of Texas at Austin
David Daly , IBM Thomas J. Watson Research Center
Lizy K. John , University of Texas at Austin
pp. 90-98

CHOP: Integrating DRAM Caches for CMP Server Platforms (Abstract)

Mike Upton , Intel
Li Zhao , Intel
Rajeev Balasubramonian , University of Utah
Ravi Iyer , Intel
Yan Solihin , North Carolina State University
Niti Madan , IBM Thomas J. Watson Research Center
pp. 99-108

Address Translation Aware Memory Consistency (Abstract)

Bogdan F. Romanescu , Duke University
Daniel J. Sorin , Duke University
Alvin R. Lebeck , Duke University
pp. 109-118

Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out (Abstract)

Dong Hyuk Woo , Intel Labs
Hsien-Hsin S. Lee , Georgia Institute of Technology
Nak Hee Seong , Georgia Institute of Technology
pp. 119-127
Micro Economics

Digital Dark Matter (Abstract)

Shane Greenstein , greenstein@kellogg.northwestern.edu
pp. 128
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