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Issue No. 06 - November/December (2010 vol. 30)
ISSN: 0272-1732
pp: 9-24
Wajahat Qadeer , Stanford University
Zain Asgar , Stanford University
Megan Wachs , Stanford University
Omid Azizi , Stanford University
Ofer Shacham , Stanford University
Stephen Richardson , Stanford University
Alex Solomatnikov , Hicamp Systems
Benjamin Lee , Duke University
John P. Stevenson , Stanford University
Mark Horowitz , Stanford University
Amin Firoozshahian , Hicamp Systems
Kyle Keley , Stanford University
<p>Because of technology scaling, power dissipation is today's major performance limiter. Moreover, the traditional way to achieve power efficiency, application-specific designs, is prohibitively expensive. These power and cost issues necessitate rethinking digital design. To reduce design costs, we need to stop building chip instances, and start making chip generators instead. Domain-specific chip generators are templates that codify designer knowledge and design trade-offs to create different application-optimized chips.</p>
Moore's Law, Dennard scaling, CMOS, ASIC, system on chip, chip multiprocessor, power efficiency, hardware generation, chip generator, hardware optimization, design methodology, RTL verification, H.264
Wajahat Qadeer, Zain Asgar, Megan Wachs, Omid Azizi, Ofer Shacham, Stephen Richardson, Alex Solomatnikov, Benjamin Lee, John P. Stevenson, Mark Horowitz, Amin Firoozshahian, Kyle Keley, "Rethinking Digital Design: Why Design Must Change", IEEE Micro, vol. 30, no. , pp. 9-24, November/December 2010, doi:10.1109/MM.2010.81
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