Pages: pp. 4-5
Abstract—Having reached the end of my second term as editor in chief, the time has come for Micro to move forward to the next phase of its evolution. I am delighted to announce that Dr. Erik Altman from IBM Research is the new Micro EIC. He has already begun making his mark on Micro, and my transition to "former EIC" has been a breeze given Erik's experience, enthusiasm, and ideas for moving Micro forward. The six articles in this issue certainly end my tenure as EIC on a high note.
Keywords—editorial board, editor in chief,
Having reached the end of my second term as editor in chief, the time has come for Micro to move forward to the next phase of its evolution. I am delighted to announce that Dr. Erik Altman from IBM Research is the new Micro EIC. Erik is an accomplished and highly respected industry architect and researcher who has held numerous leadership positions within the computing community. He has already begun making his mark on Micro, and my transition to "former EIC" has been a breeze given Erik's experience, enthusiasm, and ideas for moving Micro forward.
I also have the honor of welcoming Professor Sandhya Dwarkadas to the Micro editorial board. Sandhya is a distinguished researcher with wide-ranging expertise from microarchitecture to software systems. Her qualifications and experience are summarized in her biography.
The six articles in this issue certainly end my tenure as EIC on a high note. In the cover feature, Ofer Shacham and his colleagues argue for a new approach to design called "chip generators" that fills the void between power-inefficient general-purpose designs and expensive application-specific ones. A chip generator uses a fixed system architecture to simplify verification and software development, but encompasses domain-specific designer knowledge regarding trade-offs and the design process. The authors make a compelling case for their approach using a H.264 video encoding example.
In the next article, Christopher J. Hughes, Changkyu Kim, and Yen-Kuang Chen address the performance and energy efficiency of caches for throughput-oriented, many-core computing. They focus on the last-level cache (LLC) design and its trade-offs, including private versus shared caches and policies for replicating cache lines. The authors identify the key LLC characteristics of throughput-oriented workloads, and propose new features that better balance performance and energy than previous designs.
Amin Ansari, Shuguang Feng, Shantanu Gupta, and Scott Mahlke describe a novel approach to improving the performance of partially functional multicore chips in the third article. The idea is that faulty cores—though unable to correctly run programs—can be used to accelerate fully functional ones by providing hints to the fully operational cores. The article describes the required architectural features to make this work, and demonstrates that the approach can significantly improve average system throughput.
The article by Frederick Ryckbosch, Stijn Polfliet, and Lieven Eeckhout tackles the problem of accurate, yet fast, full-system simulation. The authors propose a CPU timing model of x86 processors that uses "interval analysis," which relates miss and misprediction events to overall performance. The article discusses several other features that improve simulator speed and accuracy, and the model is validated against a real x86 multicore processor and evaluated for different benchmarks.
In the fifth article, Luk Van Ertvelde and Lieven Eeckhout discuss four benchmarking techniques: two that reduce long benchmark runtimes while maintaining the characteristics of the full benchmark, and two that hide proprietary information that a vendor might not want to reveal while being representative of the original benchmark behavior. The article provides an excellent tutorial on these techniques, qualitatively compares them, and recommends directions for future work.
Finally, the article by Roberto Airoldi and his colleagues describe fast Fourier transform (FFT) algorithms for cognitive radio systems. The approach features algorithms that, when the available spectrum is sparse, save significant computational resources by pruning redundant multiplication and addition operations and introducing simple copy operations. Results for a multiprocessor system on chip show both significant speedups and energy savings.
It has been a privilege to serve as EIC of Micro the past four years. I have been blessed to work with an engaged and hardworking editorial board, an advisory board that offers sage advice, and a devoted staff. Due to the tireless efforts of my predecessor, Dr. Pradip Bose, Micro was in a very healthy state when I took over four years ago, and recent rankings indicate that we have been able to build on Pradip's legacy. I have no doubt that under Erik's able leadership, Micro will rise to an unprecedented level of success with the ongoing backing of the community. Please continue to support Micro—renew your subscription, encourage colleagues and employers to subscribe, write articles, propose special issues, provide constructive feedback—whatever you can do to help keep Micro vital and relevant.
I am very optimistic about the future of Micro, and tremendously grateful for your support.
Editor in Chief
Sandhya Dwarkadas is a professor of computer science at the University of Rochester, with a secondary appointment in electrical and computer engineering. She received her bachelor's degree from the Indian Institute of Technology, Madras, India, in 1986, and her MS and PhD degrees in electrical and computer engineering from Rice University in 1989 and 1993, respectively. Her research lies at the interface of hardware and software, with a particular focus on concurrency. She has authored more than 90 refereed publications that cross areas within systems. Recent projects include hardware support for transactional memory (FlexTM, RTM), on-chip cache design (DDCache, ARMCO), and operating system-level resource management for multicore processors. She is also co-inventor on seven granted US patents and has been the associate editor of IEEE Computer Architecture Letters (2006–2010) and IEEE Transactions on Parallel and Distributed Systems (2000–2003).