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Issue No. 05 - September/October (2010 vol. 30)
ISSN: 0272-1732
pp: 76-87
Vincent Gramoli , University of Neuchâtel
Per Stenstrom , Chalmers University of Technology
Ibrahim Hur , Barcelona Supercomputing Center
Martin Pohlack , Advanced Micro Devices
Sasa Tomic , Universitat Politecnica de Catalunya
Aleksandar Dragojevic , Ecole Polytechnique Federale de Lausanne
Yehuda Afek , Tel Aviv University
Adrian Cristal , Barcelona Supercomputing Center
Derin Harmanci , University of Neuchatel
Osman Unsal , Barcelona Supercomputing Center
Walther Maldonado Moreira , University of Neuchatel
Pascal Felber , University of Neuchatel
Etienne Riviere , University of Neuchatel
Guy Korland , Tel Aviv University
Martin Nowack , Technische Universitat Dresden
Rachid Guerraoui , Ecole Polytechnique Federale de Lausanne
Patrick Marlier , University of Neuchatel
Michal Kapalka , Ecole Polytechnique Federale de Lausanne
Ulrich Drepper , Red Hat
Nir Shavit , Tel Aviv University
Torvald Riegel , Technische Universitat Dresden
Michael Hohmuth , Advancd Micro Devices
Christof Fetzer , Technische Universitat Dresden
Stephan Diestelhorst , Advanced Micro Devices
The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer’s coordination methodology is considered by more and more experts as a dead-end. The transactional memory (TM) programming paradigm is a strong contender to become the approach of choice for replacing locks and implementing atomic operations in concurrent programming. Combining sequences of concurrent operations into atomic transactions allows a great reduction in the complexity of both programming and verification, by making parts of the code appear to execute sequentially without the need to program using fine-grained locking. Transactions remove from the programmer the burden of figuring out the interaction among concurrent operations that happen to conflict when accessing the same locations in memory. The EU-funded FP7 VELOX project designs, implements and evaluates an integrated TM stack, spanning from programming language to the hardware support, and including runtime and libraries, compilers, and application environments. This paper presents an overview of the VELOX TM stack and its associated challenges and contributions.
concurrent programming, software transactional memory, hardware transactional memory, compilers, language extensions
Vincent Gramoli, Per Stenstrom, Ibrahim Hur, Martin Pohlack, Sasa Tomic, Aleksandar Dragojevic, Yehuda Afek, Adrian Cristal, Derin Harmanci, Osman Unsal, Walther Maldonado Moreira, Pascal Felber, Etienne Riviere, Guy Korland, Martin Nowack, Rachid Guerraoui, Patrick Marlier, Michal Kapalka, Ulrich Drepper, Nir Shavit, Torvald Riegel, Michael Hohmuth, Christof Fetzer, Stephan Diestelhorst, "The Velox Transactional Memory Stack", IEEE Micro, vol. 30, no. , pp. 76-87, September/October 2010, doi:10.1109/MM.2010.80
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