Issue No. 05 - September/October (2010 vol. 30)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2010.82
Stefanos Kaxiras , Uppsala University, Sweden
Georgios Keramidas , Industrial Systems Institute, Greece
<p>The SARC project seeks to improve power scalability of shared-memory chip multiprocessors (CMPs) by making directory coherence more efficient in both power and performance. The authors describe how they eliminate two major sources of inefficiency for directory coherence protocols: invalidation traffic on writes and directory indirection for finding the writer.</p>
chip multiprocessors, directory cache coherence, power and performance scalability, SARC architecture
S. Kaxiras and G. Keramidas, "SARC Coherence: Scaling Directory Cache Coherence in Performance and Power," in IEEE Micro, vol. 30, no. , pp. 54-65, 2010.