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Issue No. 05 - September/October (2010 vol. 30)
ISSN: 0272-1732
pp: 30-41
Manolis Katevenis , FORTH-ICS, Heraklion
Vassilis Papaefstathiou , FORTH-ICS, Heraklion
Stamatis Kavadias , FORTH-ICS, Heraklion
Dionisios Pnevmatikatos , FORTH-ICS, Heraklion
Federico Silla , Universidad Politecnica de Valencia, Valencia
Dimitrios Nikolopoulos , FORTH-ICS, Heraklion
<p>A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.</p>
interprocessor communication, explicit communication, synchronization, configurable local memory, scratchpad, user-level RDMA, SARC

S. Kavadias, M. Katevenis, F. Silla, V. Papaefstathiou, D. Nikolopoulos and D. Pnevmatikatos, "Explicit Communication and Synchronization in SARC," in IEEE Micro, vol. 30, no. , pp. 30-41, 2010.
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