The Community for Technology Leaders
RSS Icon
Issue No.03 - May/June (2010 vol.30)
pp: 34-47
Elliott Cooper-Balis , University Of Maryland,
Bruce Jacob , U. of Maryland,
<p>This DRAM architecture optimization, which appears transparent to the memory controller, significantly reduces power consumption. With trivial additional logic, using the posted-CAS command enables a finer-grained selection when activating a portion of the DRAM array. Experiments show that, in a high-use memory system, this approach can reduce total DRAM device power consumption by up to 40 percent.</p>
DRAM, memory system, low-power design, posted-CAS command, fine-grained activation, DRAMsim
Elliott Cooper-Balis, Bruce Jacob, "Fine-Grained Activation for Power Reduction in DRAM", IEEE Micro, vol.30, no. 3, pp. 34-47, May/June 2010, doi:10.1109/MM.2010.43
1. B. Jacob, S.W. Ng, and D.T. Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2007.
2. D. Wang et al., "DRAMsim: A Memory-System Simulator," ACM SIGARCH Computer Architecture News, vol. 33, no. 4, 2005, pp. 100-107.
3. DDR2 SDRAM, part no. MT47H256M4, data sheet, Micron Technologies, 2004; dram/ddr21GbDDR2.pdf.
4. R.J. Baker, CMOS Circuit Design, Layout, and Simulation, 2nd ed., Wiley-IEEE Press, 2005.
5. B. Keeth et al., DRAM Circuit Design: Fundamental and High-Speed Topics, 2nd ed., Wiley-IEEE Press, 2007.
6. "Calculating Memory System Power for DDR2," tech. note TN-47-04, Micron Technologies, 2005; ddr2tn4704.pdf.
7. 128 M-Bit (4-Bank × 1 M-Word × 32-Bit) Single Data Rate I/F FCRAM, part no. MB81ES123245-10, data sheet DS05-11440-2E, Fujitsu, 2006; http://www.datasheetdir.comMB81ES123245-10+download .
8. R. Saied and C. Chakrabarti, "Scheduling for Minimizing the Number of Memory Accesses in Low Power Applications," Proc. Workshop VLSI Signal Processing, IEEE Press, 1996, pp. 169-178.
9. L. Mason, "Low Power DRAM Roadmap Faces Rocky Road and Fuzzy Guardrails," Denali Memory Report, blog, 27 June 2008; dmr/2008/06/27low_power_dram_roadmap_faces_rocky_road_ .
10. B. Davis, B. Jacob, and T. Mudge, "The New DRAM Interfaces: SDRAM, RDRAM, and Variants," Proc. High Performance Computing, LNCS 1940, Springer, 2000, pp. 26-31.
11. V. Cuppu and B. Jacob, "Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?" Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01), ACM Press, 2001, pp. 62-71.
16 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool