Issue No. 03 - May/June (2010 vol. 30)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2010.43
Elliott Cooper-Balis , University Of Maryland,
Bruce Jacob , U. of Maryland,
<p>This DRAM architecture optimization, which appears transparent to the memory controller, significantly reduces power consumption. With trivial additional logic, using the posted-CAS command enables a finer-grained selection when activating a portion of the DRAM array. Experiments show that, in a high-use memory system, this approach can reduce total DRAM device power consumption by up to 40 percent.</p>
DRAM, memory system, low-power design, posted-CAS command, fine-grained activation, DRAMsim
B. Jacob and E. Cooper-Balis, "Fine-Grained Activation for Power Reduction in DRAM," in IEEE Micro, vol. 30, no. , pp. 34-47, 2010.