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Issue No. 02 - March/April (2010 vol. 30)
ISSN: 0272-1732
pp: 16-29
Bill Hughes , Advanced Micro Devices
Nathan Kalyanasundharam , Advanced Micro Devices
Pat Conway , Advanced Micro Devices
Gregg Donley , Advanced Micro Devices
Kevin Lepak , Advanced Micro Devices
<p>The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.</p>
processor, x86-64, multiprocessor, memory hierarchy, cache, cache directory, probe filter, system interconnect, HyperTransport3 technology, blade server, power envelopes
Bill Hughes, Nathan Kalyanasundharam, Pat Conway, Gregg Donley, Kevin Lepak, "Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor", IEEE Micro, vol. 30, no. , pp. 16-29, March/April 2010, doi:10.1109/MM.2010.31
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