The Community for Technology Leaders
RSS Icon
Issue No.01 - January/February (2010 vol.30)
pp: 40-49
Joseph Devietti , University of Washington
Brandon Lucia , University of Washington
Luis Ceze , University of Washington
Mark Oskin , University of Washington
<p>Shared-memory multicore and multiprocessor systems are nondeterministic, which frustrates debugging and complicates testing of multithreaded code, impeding parallel programming's widespread adoption. The authors propose fully deterministic shared-memory multiprocessing that not only enhances debugging by offering repeatability by default, but also improves the quality of testing and the deployment of production code. They show that determinism can be provided with little performance cost on future hardware.</p>
multiprocessors, determinism, debugging, reliability
Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin, "DMP: Deterministic Shared-Memory Multiprocessing", IEEE Micro, vol.30, no. 1, pp. 40-49, January/February 2010, doi:10.1109/MM.2010.14
1. D.F. Bacon and S.C. Goldstein, "Hardware-Assisted Replay of Multiprocessor Programs," Proc. 1991 ACM/ONR Workshop Parallel and Distributed Debugging, ACM Press, 1991, pp. 194-206.
2. P. Montesinos, L. Ceze, and J. Torrellas, "DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently," Proc. 35th Int'l Symp. Computer Architecture (ISCA 08), IEEE CS Press, 2008, pp. 289-300.
3. S. Narayanasamy, C. Pereira, and B. Calder, "Recording Shared Memory Dependencies Using Strata," Proc. 12th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 06), ACM Press, 2006, pp. 229-240.
4. M. Ronsee and K. De Bosschere, "RecPlay: A Fully Integrated Practical Record/Replay System," ACM Trans. Computer Systems, vol. 17, no. 2, 1999, pp. 133-152.
5. M. Xu, R. Bodik, and M.D. Hill, "A 'Flight Data Recorder' for Enabling Full-System Multiprocessor Deterministic Replay," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 122-135.
6. T. Bergan et al., "CoreDet: A Compiler and Runtime System for Deterministic Multithreaded Execution," to be presented at 15th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 2010, asplos10-coredet.pdf.
7. L. Hammond et al., "Transactional Memory Coherence and Consistency," Proc. 31st Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 102-114.
8. M. Herlihy and J.E.B. Moss, "Transactional Memory: Architectural Support for Lock-Free Data Structures," Proc. 20th Int'l Symp. Computer Architecture (ISCA 93), IEEE CS Press, 1993, pp. 289-300.
9. J. Devietti et al., "DMP: Deterministic Shared Memory Multiprocessing," Proc. 14th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 09), ACM Press, 2009, pp. 85-96.
10. S. Gopal et al., "Speculative Versioning Cache," Proc. 4th Int'l Symp. High-Performance Computer Architecture (HPCA 98), IEEE CS Press, 1998, pp. 195-205.
11. C.K. Luk et al., "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," Proc. 2005 ACM SIGPLAN Conf. Programming Language Design and Implementation, ACM Press, 2005, pp. 190-200.
12. S. Woo et al., "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Int'l Symp. Computer Architecture (ISCA 95), IEEE CS Press, 1995, pp. 24-36.
13. C. Bienia et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," Proc. 17th Int'l Conf. Parallel Architectures and Compilation Techniques, ACM Press, 2008, pp. 72-81.
50 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool