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Issue No.01 - January/February (2010 vol.30)
pp: 29-39
John H. Kelm , University of Illinois at Urbana-Champaign
Daniel R. Johnson , University of Illinois at Urbana-Champaign
Steven S. Lumetta , University of Illinois at Urbana-Champaign
Sanjay J. Patel , University of Illinois at Urbana-Champaign
<p>This article presents a memory model for parallel compute accelerators with task-based programming models that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single address space view of memory without requiring hardware cache coherence. The memory model supports visual computing applications, which are becoming an important class of workloads capable of exploiting 1,000-core processors.</p>
accelerator, memory model, parallel architecture, software coherence
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank, "A Task-Centric Memory Model for Scalable Accelerator Architectures", IEEE Micro, vol.30, no. 1, pp. 29-39, January/February 2010, doi:10.1109/MM.2010.6
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