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Issue No. 06 - November/December (2009 vol. 29)
ISSN: 0272-1732
pp: 5-6
Makoto Ikeda , University of Tokyo
Fumio Arakawa , Renesas Technology

Low-power and high-speed chips ( Cool Chips) encompass a broad range of architectures, applications, methodologies, and usage models. These technologies are present in multimedia, digital consumer electronics, mobile, graphics, encryption, robotics, networking, and biometrics. They are based on multiprocessing, reconfigurable computing, dependable computing, and memory architectures. Cool software, which includes binary translators and compilers, is also emerging.
These technologies all aim to reduce power consumption and enhance chip performance. Regardless of their goals, all of industry has been challenged with developing optimal solutions—both hardware and software—for power optimization according to the required performance. In general, in an attempt to migrate decades' worth of legacy approaches to low-power technology, industry approaches these optimal solutions from the perspective of starting from scratch.
With this in mind, we've been organizing annual Cool Chips conferences since 1998. We celebrated Cool Chips XII in April 2009. Cool Chips, a sister conference to Hot Chips, focuses on all aspects of cool technologies. Approximately 150 individuals attend the conference. In addition to regular paper presentations, the conference includes keynote and invited talks, special topic sessions, and poster and panel discussions. To attract submissions from engineers working in industry, the program committee bases acceptance on a short abstract. The conference proceedings include only the short abstract with the final presentation rather than a set of long papers. All members of the program committee reviewed each of the 33 submissions for Cool Chips XII and selected the best 16 based on technical merit and innovation.
The articles
This special issue of IEEE Micro captures five contributions from among 12 submissions—not only from Cool Chips presentations but also from ordinal submissions. Multicore, video codec, and recognition processors were major topics at Cool Chips XII, and the articles selected for this issue reflect this trend.
In "Domain Partitioning Technology for Embedded Multicore Processors," Tohru Nojiri of Hitachi and his colleagues from Hitachi, Renesas Technology, and the Tokyo Institute of Technology describe a domain-partitioning mechanism based on physical partition techniques. This mechanism isolates unintentional access to resources assigned to other domains for multiple operating systems on an embedded multicore processor. The authors evaluated the techniques on prototype and product chips with 90-nm and 65-nm CMOS process technologies. The results show negligible impact on area and speed.
In "A Full HD Multistandard Video Codec for Mobile Applications," Motoki Kimura and his colleagues from Renesas Technology describe a full high-definition (full HD) multistandard codec based on a stream processing unit. This unit consists of a two-way very long instruction word (VLIW) stream processor and a CABAC accelerator. The video codec achieves a performance of 40 Mbps at 162 MHz and power consumption of 176 mW in real-time H.264 full HD video decoding using 65-nm CMOS.
In "Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining," Joo-Young Kim and his colleagues from the Korea Advanced Institute of Science and Technology (KAIST) describe an energy-efficient object recognition processor. The processor uses a neuro-fuzzy controller for intelligent region-of-interest estimation, workload-aware task scheduling, applied database size control, and workload-aware dynamic power management. It achieves 8.2-mJ per frame energy consumption for 60 frames-per-second object recognition for VGA-size video input in a 0.13-μm CMOS.
In "Architecture Design of Versatile Recognition Processor for Sensornet Applications," Yuichi Hori and his colleagues from Keio University describe a versatile and low-power recognition processor employing a Haar-like feature and cascaded classifier. The design optimization results in power consumption as low as 0.15 μW/fps at 0.9V in 90-nm CMOS.
In "A QVGA-Size Pixel-Parallel Image Processor for 1,000-fps Vision," Takeshi Komuro and his colleagues from the University of Tokyo describe a massively parallel image processor. By processing as many processing elements as pixels, it achieves a real-time vision system for object identification and pose estimation. The processor provides more accurate and robust robot control with frame rates as high as 1,000 fps. Pipelined bit-serial adders in dynamic logic with delayed clocks enable high-speed and low-power operation of 42 mW with 320 × 240 (QVGA) processing elements. At 50-MHz operating frequency, the pixel-parallel image processor achieves calculation speeds of up to 980,000 and 490,000 times per second, respectively, for 1st- and 2nd-order moments in 0.35-μm CMOS.
It has been a pleasure to put together this special issue of IEEE Micro on Cool Chips. We thank Editor-in-Chief David Albonesi, managing editor Joan Taylor, and the IEEE Micro staff for their support and guidance. We also thank Tadao Nakamura, conference chair of Cool Chips 2009, for his help in arranging this special issue. The issue would not have been possible without their help.
Makoto Ikeda is an associate professor in the VLSI Design and Education Center at the University of Tokyo. His research interests include high-performance, low-power, and reliable digital circuit and smart image sensor design. He is a program committee co-chair of the Cool Chips conference series, and a program committee member of the International Solid-State Circuits Conference, VLSI Circuits Symposium, Asian Solid-State Circuits Conference, International Symposium on Quality Electronic Design, and International Conference on Field Programmable Technology. Ikeda has a PhD in electrical engineering from the University of Tokyo.
Fumio Arakawa is a chief engineer of microprocessors in the System Core Technology Division of Renesas Technology Corp., Tokyo. He serves as a program committee co-chair of the Cool Chips conference series. Arakawa has a PhD in electrical engineering from the University of Tokyo. He is a member of the Institute of Electronics, Information, and Communication Engineers and the IEEE.
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