The Community for Technology Leaders


Pages: pp. 4

In the article, "Dynamic Multicore Resource Management: A Machine Learning Approach," by José F. Martínez and Engen Ipek ( IEEE Micro, November/December 2009), an important reference was inadvertently omitted. The missing reference (Nesbit et al. 2006) was meant to be cited on page 13. The correct version appears below.

Case 2: Multiresource allocation

Although resources that are relatively independent of one another can be managed in isolation, many shared resources on multicore systems interact. Unrestricted sharing of microarchitectural resources can lead to destructive interference. Although several proposals that address the management of a single microarchitectural resource exist in the literature, proposals to manage multiple interacting resources on multicore chips at runtime are much scarcer.

Consider, for example, the case of a multicore system in which the on-chip L2 cache space, off-chip bandwidth, and the chip's power budget are shared among applications, and each resource's use is regulated via an independent QoS knob. As the amount of one resource allocated to an application changes, the application's demands on the other resources also change. For example, increasing an application's allocated cache space can cause its working set to fit in the cache, and can dramatically reduce its off-chip bandwidth demand (which could in turn be allocated to other applications with higher demand). Similarly, increasing an application's power budget could cause it to run at a higher frequency and to demand more bandwidth. Hence, the optimal allocation of one resource type depends in part on the allocated amounts of other resources, requiring a coordinated resource-management scheme for optimal performance.

Figure 5 shows an example of performance loss due to uncoordinated resource management in a multicore system incorporating three QoS knobs for regulating the system's shared cache, off-chip bandwidth, and power budget. 10,11,16 A four-application, desktop-style multiprogrammed workload is executed on a quadcore chip with an associated DDR2-800 memory subsystem. The figure compares configurations that allocate one or more of the resources in an uncoordinated fashion to a static, fair-share allocation of the resources, as well as an unmanaged sharing scenario in which all applications can access all resources at all times. In this workload, unmanaged resource sharing delivers considerable slowdowns even when compared to a rigid, static resource distribution among the cores (Fair-Share). Moreover, managing a subset of the resources in an uncoordinated fashion is inferior to static partitioning, indicating that resource interactions render individual adaptive management policies largely ineffective.


  • 1. C.Isciet al.,"An Analysis of Efficient Multi-core Global Power Management Policies: Maximizing Performance for a Given Power Budget,"Proc. Int'l Symp. Microarchitecture(MICRO 06), IEEE CS Press,2006,pp. 347-358.
  • 2. M.QureshiandY.Patt"Utility-based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,"Proc. Int'l Symp. Microarchitecture(MICRO 06), IEEE CS Press,2006,pp. 423-432.
  • 3. K.J.Nesbitet al.,"Fair Queueing Memory Systems,"Proc. Int'l Symp. Microarchitecture(MICRO 06), IEEE CS Press,2006,pp. 208-222.

55 ms
(Ver 3.x)