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Issue No. 04 - July/August (2009 vol. 29)
ISSN: 0272-1732
pp: 8-21
Henry I. Smith , Massachusetts Institute of Technology
Jason Orcutt , Massachusetts Institute of Technology
Krste Asanović , University of California, Berkeley
Hanqing Li , Massachusetts Institute of Technology
Benjamin Moss , Massachusetts Institute of Technology
Franz X. Kärtner , Massachusetts Institute of Technology
Christopher Batten , Massachusetts Institute of Technology
Miloš A. Popović , Massachusetts Institute of Technology
Judy L. Hoyt , Massachusetts Institute of Technology
Ajay Joshi , Massachusetts Institute of Technology
Vladimir Stojanović , Massachusetts Institute of Technology
Anatol Khilo , Massachusetts Institute of Technology
Charles W. Holzwarth , Massachusetts Institute of Technology
Rajeev J. Ram , Massachusetts Institute of Technology
ABSTRACT
<p>Silicon photonics is a promising technology for addressing memory bandwidth limitations in future many-core processors. This article first introduces a new monolithic silicon-photonic technology, which uses a standard bulk CMOS process to reduce costs and improve energy efficiency, and then explores the logical and physical implications of leveraging this technology in processor-to-memory networks.</p>
INDEX TERMS
silicon-photonic technology, multicore/many-core processors, on-chip interconnection networks, processor-to-DRAM networks, hardware
CITATION
Henry I. Smith, Jason Orcutt, Krste Asanović, Hanqing Li, Benjamin Moss, Franz X. Kärtner, Christopher Batten, Miloš A. Popović, Judy L. Hoyt, Ajay Joshi, Vladimir Stojanović, Anatol Khilo, Charles W. Holzwarth, Rajeev J. Ram, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics", IEEE Micro, vol. 29, no. , pp. 8-21, July/August 2009, doi:10.1109/MM.2009.60
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