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Issue No. 03 - May/June (2009 vol. 29)
ISSN: 0272-1732
pp: 20-30
Jiang Xu , Hong Kong University of Science and Technology
Wayne Wolf , Georgia Institute of Technology
Wei Zhang , Princeton University
ABSTRACT
<p>DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.</p>
INDEX TERMS
network on chip, multiprocessor, system on chip, asynchronous, wave pipeline, low power, double data rate, interconnect
CITATION

W. Zhang, W. Wolf and J. Xu, "Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs," in IEEE Micro, vol. 29, no. , pp. 20-30, 2009.
doi:10.1109/MM.2009.40
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