Issue No. 01 - January/February (2009 vol. 29)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2009.13
Xiaoyao Liang , Harvard University
Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
<p>Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The Revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.</p>
process variations, voltage interpolation, variable latency
X. Liang, D. Brooks and G. Wei, "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency," in IEEE Micro, vol. 29, no. , pp. 127-138, 2009.