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Issue No.01 - January/February (2009 vol.29)
pp: 127-138
Xiaoyao Liang , Harvard University
Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
<p>Process variations will significantly degrade the performance benefits of future microprocessors as they move toward nanoscale technology. Device parameter fluctuations can introduce large variations in peak operation among chips, cores on a single chip, and microarchitectural blocks within one core. The Revival technique combines the post-fabrication tuning techniques voltage interpolation (VI) and variable latency (VL) to reduce such frequency variations.</p>
process variations, voltage interpolation, variable latency
Xiaoyao Liang, Gu-Yeon Wei, David Brooks, "Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency", IEEE Micro, vol.29, no. 1, pp. 127-138, January/February 2009, doi:10.1109/MM.2009.13
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16. X. Liang, D. Brooks, and G.-Y. Wei, "A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2008, pp. 404-405.
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19. A. Agarwal et al., "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Trans. Very Large Scale Integration Systems, vol. 13, no. 1, Jan. 2005, pp. 27-38.
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