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Issue No. 01 - January/February (2009 vol. 29)
ISSN: 0272-1732
pp: 84-95
Luis Ceze , University of Washington
Josep Torrellas , University of Illinois, Urbana-Champaign
James Tuck , North Carolina State University
Wonsun Ahn , University of Illinois, Urbana-Champaign
ABSTRACT
<p>Many code analysis techniques for optimization, debugging, and parallelization must perform runtime disambiguation of address sets. Hardware signatures support such operations efficiently and with low complexity. SoftSig exposes hardware signatures to software through instructions that control which addresses to collect and which to disambiguate against. The Memoise algorithm demonstrates SoftSig's versatility by detecting and eliminating redundant function calls. DOI of original article is available at http://doi.acm.org/10.1145/1346281.1346300 </p>
INDEX TERMS
memory disambiguation, multicore architectures, runtime optimization
CITATION
Luis Ceze, Josep Torrellas, James Tuck, Wonsun Ahn, "SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization", IEEE Micro, vol. 29, no. , pp. 84-95, January/February 2009, doi:10.1109/MM.2009.15
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